Semiconductor device including single crystal semiconductor pattern with complementary structure

Patent metadata

Field	Value
Publication number	US-12593440-B2
Application number	US-202318200135-A
Country	US
Kind code	B2
Filing date	May 22, 2023
Priority date	May 24, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher vertical level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; a complementary structure in contact with and at the same vertical level along a horizontal plane as a second side surface of the first single crystal semiconductor pattern at a level of the first vertical channel region; and a lower conductive line disposed below the first single crystal semiconductor pattern, the first gate electrode, and the complementary structure, wherein the complementary structure includes an oxide semiconductor layer, wherein the lower conductive line extends in a first direction and is electrically connected to the first single crystal semiconductor pattern, and wherein the first single crystal semiconductor pattern is disposed, in the first direction and at the vertical level along the horizontal plane, between the complementary structure and the first gate electrode.

2 . The semiconductor device as claimed in claim 1 , wherein the first single crystal semiconductor pattern is a single crystal silicon pattern, and wherein the oxide semiconductor layer includes indium and/or zinc.

3 . The semiconductor device as claimed in claim 1 , wherein the oxide semiconductor layer of the complementary structure is in contact with the first single crystal semiconductor pattern.

4 . The semiconductor device as claimed in claim 1 , wherein the first side surface and the second side surface of the first single crystal semiconductor pattern oppose each other.

5 . The semiconductor device as claimed in claim 1 , wherein the oxide semiconductor layer of the complementary structure has an energy band gap greater than an energy band gap of the first single crystal semiconductor pattern.

6 . The semiconductor device as claimed in claim 1 , further comprising:
a second single crystal semiconductor pattern at the same vertical level as the first single crystal semiconductor pattern; a second gate electrode parallel to the first gate electrode; and a second gate dielectric layer, the second gate dielectric layer including a portion between the second gate electrode and the second single crystal semiconductor pattern, wherein: a portion of a structure including the first single crystal semiconductor pattern, the complementary structure, and the second single crystal semiconductor pattern all at the same vertical level as each other along the horizontal plane is between the first gate electrode and the second gate electrode at the same vertical level as the first gate electrode and the second gate electrode along the horizontal plane, the complementary structure is between the first single crystal semiconductor pattern and the second single crystal semiconductor pattern, the second single crystal semiconductor pattern includes a third source/drain region, a fourth source/drain region, and a second vertical channel region between the third and fourth source/drain regions, and the fourth source/drain region is at a higher vertical level than the third source/drain region.

7 . The semiconductor device as claimed in claim 6 , wherein:
an upper surface of each of the first single crystal semiconductor pattern and the second single crystal semiconductor pattern is at a higher vertical level than an upper surface of each of the first gate electrode and the second gate electrode, and a lower surface of each of the first single crystal semiconductor pattern and the second single crystal semiconductor pattern is at a lower vertical level than a lower surface of each of the first gate electrode and the second gate electrode.

8 . The semiconductor device as claimed in claim 6 , wherein the oxide semiconductor layer of the complementary structure includes at least two layers having different energy band gaps.

9 . The semiconductor device as claimed in claim 6 , wherein:
the complementary structure further includes an insulating layer in contact with the oxide semiconductor layer, the insulating layer is between the first single crystal semiconductor pattern and the second single crystal semiconductor pattern, and the oxide semiconductor layer includes:
a first oxide semiconductor portion between the first single crystal semiconductor pattern and the insulating layer, and
a second oxide semiconductor portion between the second single crystal semiconductor pattern and the insulating layer.

10 . The semiconductor device as claimed in claim 9 , wherein:
the complementary structure further includes an intermediate shielding conductive line, the intermediate shielding conductive line is between the first single crystal semiconductor pattern and the second single crystal semiconductor pattern, and the intermediate shielding conductive line is spaced apart from the oxide semiconductor layer of the complementary structure by the insulating layer.

11 . The semiconductor device as claimed in claim 1 , further comprising:
a data storage structure at a higher vertical level than that of the first gate electrode and at a higher vertical level than that of the first single crystal semiconductor pattern.

12 . The semiconductor device as claimed in claim 11 , further comprising:
a lower contact structure between the first source/drain region and the lower conductive line, the lower contact structure electrically connecting the first source/drain region and the lower conductive line to each other; and an upper contact structure between the second source/drain region and the data storage structure, the upper contact structure electrically connecting the second source/drain region and the data storage structure to each other.

13 . The semiconductor device as claimed in claim 11 , wherein the data storage structure is a Dynamic Random Access Memory (DRAM) capacitor configured to store data on a DRAM or a ferroelectric capacitor configured to store data on a ferroelectric Random Access Memory.

14 . A semiconductor device, comprising:
a first conductive line and a second conductive line at a first vertical level, the first conductive line and the second conductive line being parallel to each other; a first single crystal semiconductor pattern and a second single crystal semiconductor pattern at the first vertical level and spaced apart from each other; a complementary structure between the first single crystal semiconductor pattern and the second single crystal semiconductor pattern in a first direction, the complementary structure including an oxide semiconductor layer; and lower conductive line disposed below the first conductive line, the second conductive line, the first single crystal semiconductor pattern, the second single crystal semiconductor pattern, and the complementary structure, wherein the first single crystal semiconductor pattern, the second single crystal semiconductor pattern, and the complementary structure are between the first conductive line and the second conductive line along a horizontal plane at the first vertical level, and wherein the lower conductive line extends in the first direction and is electrically connected to the first s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeonil
• Lee Kyunghwan
• Cho Min Hee

Classifications

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10B12/485

  Bit line contacts · CPC title

• H10B53/30

  characterised by the memory core region · CPC title

• H10B53/10

  characterised by the top-view layout · CPC title

• H10B12/482

  Bit lines · CPC title