Devices and systems with string drivers including high band gap material and methods of formation

Patent metadata

Field	Value
Publication number	US-11018255-B2
Application number	US-201816110217-A
Country	US
Kind code	B2
Filing date	Aug 23, 2018
Priority date	Aug 29, 2017
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

First claim

What is claimed is:

1. A device comprising a string driver, the string driver comprising:
at least one pillar extending vertically between a pair of electrodes, the at least one pillar comprising:
a channel region between a drain region and a source region; and
a dielectric material in a central portion of the at least one pillar, the channel region laterally surrounding the dielectric material,
wherein at least one of the channel region, the drain region, and the source region comprises a high band gap material; and

only one gate region laterally surrounding the channel region of a pillar of the at least one pillar, the gate region comprising an electrically conductive material and spaced from the high band gap material,
wherein each electrode, of the pair of electrodes, comprises a vertically extending portion surrounding by a portion of the high band gap material.

2. The device of claim 1 , wherein the high band gap material is selected from the group consisting of zinc oxide, indium gallium zinc oxide, indium zinc oxide, silicon carbide, tin oxide, and gallium arsenide.

3. The device of claim 2 , wherein the high band gap material comprises amorphous indium gallium zinc oxide.

4. The device of claim 1 , wherein the channel region comprises the high band gap material.

5. The device of claim 4 , further comprising another dielectric material spacing the high band gap material of the channel region from the gate region.

6. The device of claim 1 , wherein the drain region and the source region are each spaced from the channel region by an offset region of about 0 micrometers (about 0 μm).

7. The device of claim 1 , wherein the channel region comprises the high band gap material and another high band gap material laterally surrounding the dielectric material.

8. The device of claim 1 , wherein the at least one pillar comprises:
a pillar comprising the channel region, the drain region, and the source region; and
another pillar comprising another channel region, another drain region, and another source region, at least one of the other channel region, the other drain region, and the other source region comprising the high band gap material,
the gate region laterally surrounding the channel region and the other channel region.

9. The device of claim 1 , wherein:
the channel region comprises the high band gap material;
the channel region further comprises another high band gap material laterally between the high band gap material and the gate region; and
the gate region laterally surrounds both the high band gap material and the other high band gap material.

10. The device of claim 1 , wherein the vertically extending portion of each electrode, of the pair of electrodes, extends vertically past an end of the gate region.

11. The device of claim 1 , wherein the drain region and the source region are each spaced from the channel region by an offset region of less than 0.2 micrometers (less than 0.2μm) but greater than 0.1 micrometers (greater than 0.1μm).

12. A device, comprising:
an array of charge storage devices;
access lines in operable communication with the array of charge storage devices; and
a string driver in operable communication with at least one access line of the access lines, the string driver comprising:
at least one pillar extending vertically between a pair of electrodes, the at least one pillar comprising:
a channel region between a drain region and a source region; and
a dielectric material in a central portion of the at least one pillar, the channel region laterally surrounding the dielectric material,
wherein at least one of the channel region, the drain region, and the source region comprises a high band gap material; and

only one gate region laterally surrounding the channel region of a pillar of the at least one pillar, the gate region comprising an electrically conductive material and spaced from the high band gap material,

wherein each electrode, of the pair of electrodes, comprises a vertically extending portion surrounded by a portion of the high band gap material.

13. The device of claim 12 , wherein the array of charge storage devices is a three-dimensional NAND array comprising a plurality of stacked tiers of the charge storage devices.

14. The device of claim 12 , wherein the string driver comprises a plurality of the pillars of the at least one pillar, the one gate region laterally surrounding the channel regions of the pillars of the plurality.

15. The device of claim 12 , wherein:
the source region comprises the high band gap material doped with at least one dopant; and
the drain region comprises the high band gap material doped with the at least one dopant,
the at least one dopant selected from the group consisting of aluminum (Al) and silicon (Si).

16. A system, comprising:
an array of non-volatile memory devices;
at least one string driver in operable communication with the array, a string driver, of the at least one string driver, comprising:
at least one pillar extending vertically between a pair of electrodes, the at least one pillar comprising:
a channel region between a drain region and a source region; and
a dielectric material in a central portion of the at least one pillar, the channel region laterally surrounding the dielectric material,
wherein at least one of the channel region, the drain region, and the source region comprises a high band gap material; and

only one gate region laterally surrounding the channel region of a pillar of the at least one pillar, the gate region comprising an electrically conductive material and spaced from the high band gap material,

wherein each electrode, of the pair of electrodes, comprises a vertically extending portion surrounded by a portion of the high band gap material; and
at least one peripheral device in operable communication with the array of non-volatile memory devices, the at least one peripheral device comprising circuitry in operable communication with the at least one string driver.

17. A method of forming a string driver, the method comprising:
forming, on an electrode over a base material, a pillar comprising a dielectric material in a central portion of the pillar and comprising a high band gap material laterally surrounding the dielectric material;
forming another dielectric material adjacent the high band gap material; and
forming a region of an electrically conductive material adjacent the other dielectric material, the region of the electrically conductive material spaced from the high band gap material by at least the other dielectric material;
forming another electrode on the pillar,
wherein the pillar extends vertically between a pair of electrodes, the pair of electrodes comprising the electrode and the other electrode, the pillar comprising:
a channel region between a drain region and a source region; and
the dielectric material in the central portion of the pillar, the channel region laterally surrounding the dielectric material,

wherein at least one of the channel region, the drain region, and the source region of the string driver comprises the high band gap material,
wherein the string driver comprises only one gate region laterally surrounding the channel region of the pillar, the gate region comprising the electrically conductive material,
wherein the gate region is spaced from the high band gap material, and
wherein each electrode, of the pair of electrodes, comprises a vertically extending portion surrounded by a portion of the high band gap material.

18. The method of claim 17 ,

Assignees

• Micron Technology Inc

Inventors

• Liu Haitao
• Huang Guangyu
• Mouli Chandra V
• Goda Akira
• Pandey Deepak Chandra
• Karda Kamal M

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title