Determining a correlation between power disturbances and data errors in a test system

Patent metadata

Field	Value
Publication number	US-12591007-B2
Application number	US-202218079685-A
Country	US
Kind code	B2
Filing date	Dec 12, 2022
Priority date	Dec 12, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT, and to compare the first data and the second data to determine if there is a correlation between the power disturbance and the error.

First claim

What is claimed is:

1 . Automatic test equipment (ATE) for testing a device under test (DUT), the ATE comprising:
a power supply configured to supply power to the DUT: one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify one or more bit errors in the first data, the first data representing operation of the DUT or an individual component of the DUT based on application of test data to the DUT; and a power supply controller configured to receive second data representing a power disturbance in the power supplied to the DUT, the power disturbance comprising a deviation in output of power from the power supply from a predefined norm, and the power disturbance not being intentionally inflicted; wherein the one or more processing devices are further configured to determine whether the DUT passed or failed testing based on the first data, to compare the first data and the second data to determine if there is a correlation between the power disturbance and the one or more bit errors, and to report to a user or computing system that the first data on which the testing is based contains bit errors that correlate to the power disturbance in the power supply.

2 . The ATE of claim 1 , wherein the power supply is configured to operate at voltage levels margined around a nominal voltage of the DUT.

3 . The ATE of claim 1 , wherein the power supply controller is configured to manage voltage levels at the power supply.

4 . The ATE of claim 1 , wherein the power supply is configured to have current limits margined around a maximum current draw of the DUT.

5 . The ATE of claim 1 , wherein the power supply controller is configured to manage current levels at the power supply.

6 . The ATE of claim 1 , wherein the one or more processing devices are configured to issue commands to the power supply controller to control the power supplied by the power supply to the DUT.

7 . The ATE of claim 1 , wherein the power supply controller is configured to receive the second data from the power supply.

8 . The ATE of claim 7 , wherein the power supply controller is configured to timestamp the second data.

9 . The ATE of claim 8 , wherein the power supply controller is configured to send the timestamped second data to the one or more processing devices.

10 . The ATE of claim 1 , wherein the power supply controller is configured to store the second data in memory.

11 . The ATE of claim 1 , wherein the one or more processing devices are configured to store the first data in memory.

12 . The ATE of claim 1 , wherein the one or more processing devices are configured to timestamp the first data.

13 . The ATE of claim 12 , wherein the one or more processing devices are configured to send the time-stamped first data to the power supply controller.

14 . The ATE of claim 1 , wherein the one or more processing devices are configured to use bit error testing to test for the one or more bit errors.

15 . The ATE of claim 1 , wherein the communication channel comprises a peripheral component interconnect express (PCIe) bus or Ethernet.

16 . The ATE of claim 1 , wherein the one or more processing devices are configured to control an ambient temperature around the DUT so that the ambient temperature changes from below freezing to above freezing but below a maximum operating temperature of the DUT.

17 . The ATE of claim 1 , wherein the one or more processing devices are configured to control a bandwidth of the communication channel.

18 . A method for testing a device under test (DUT) using automatic test equipment (ATE), the method comprising:
receiving first data from the DUT over a communication channel, the first data representing operation of the DUT or an individual component of the DUT based on application of test data to the DUT; determining whether the DUT passed or failed testing based on the first data; analyzing the first data to identify one or more bit errors in the first data; receiving second data representing a power disturbance in power supplied to the DUT by a power supply, the power disturbance comprising a deviation in output of power from the power supply from a predefined norm, and the power disturbance not being intentionally inflicted; comparing the first data and the second data to determine if there is a correlation between the power disturbance and the one or more bit errors; and reporting to a user or computing system that the first data on which the testing is based contains bit errors that correlate to the power disturbance in the power supply.

19 . The method of claim 18 , wherein supplying power to the DUT comprises operating the power supply at voltage levels margined around a nominal voltage of the DUT.

20 . The method of claim 18 , further comprising managing voltage levels at the power supply.

21 . The method of claim 18 , wherein the power supply is configured to have current limits margined around a maximum current draw of the DUT.

22 . The method of claim 18 , further comprising managing current levels at the power supply.

23 . The method of claim 18 , further comprising issuing commands to a power supply controller to control the power supplied by the power supply to the DUT.

24 . The method of claim 18 , wherein receiving the second data comprises receiving the second data from the power supply.

25 . The method of claim 24 , further comprising timestamping the second data.

26 . The method of claim 25 , further comprising sending, using a power supply controller, the timestamped second data to one or more processing devices.

27 . The method of claim 18 , further comprising storing, using a power supply controller, the second data in memory.

28 . The method of claim 18 , further comprising storing the first data in memory.

29 . The method of claim 18 , further comprising timestamping the first data.

30 . The method of claim 29 , further comprising sending the timestamped first data to a power supply controller.

31 . The method of claim 18 , further comprising testing, using bit error testing, for the one or more bit errors.

32 . The method of claim 18 , wherein the communication channel comprises a peripheral component interconnect express (PCIe) bus or Ethernet.

33 . The method of claim 18 , further comprising controlling an ambient temperature around the DUT so that the ambient temperature changes from below freezing to above freezing but below a maximum operating temperature of the DUT.

34 . The method of claim 18 , further comprising controlling a bandwidth of the communication channel and wherein comparing comprises detecting correlations between power disturbances and bit errors in the communication channel based on the bandwidth.

Assignees

• Teradyne Inc

Inventors

• Jones Christopher C

Classifications

• G01R31/2879 Primary

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/3171

  BER [Bit Error Rate] test · CPC title

• G01R19/30

  Measuring the maximum or the minimum value of current or voltage reached in a time interval (G01R19/04 takes precedence) · CPC title

• G01R31/3173

  Marginal testing · CPC title

• G01R31/31708

  Analysis of signal quality (G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20) · CPC title