Semiconductor package

Patent metadata

Field	Value
Publication number	US-12588567-B2
Application number	US-202318356289-A
Country	US
Kind code	B2
Filing date	Jul 21, 2023
Priority date	Jul 26, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a first semiconductor chip; a plurality of second semiconductor chips stacked on the first semiconductor chip, the plurality of second semiconductor chips respectively having widths narrower than a width of the first semiconductor chip; and a molded layer on an upper surface of the first semiconductor chip, the molded layer on side surfaces of the plurality of second semiconductor chips, wherein the first semiconductor chip includes: a first semiconductor substrate, a first semiconductor device layer on a front surface of the first semiconductor substrate, first front-surface pads on the first semiconductor device layer, a first back-surface insulating layer on a back surface of the first semiconductor substrate and divided into a first region and a second region, first back-surface pads in the first region of the first back-surface insulating layer, dummy pads in the second region of the first back-surface insulating layer, the dummy pads respectively having an upper surface with a metal oxide film thereon, and a first through-electrode extending through the first semiconductor substrate and electrically connecting the first front-surface pads and the first back-surface pads to each other, wherein the plurality of second semiconductor chips respectively includes: a second semiconductor substrate, a second semiconductor device layer on a front surface of the second semiconductor substrate, a second front-surface insulating layer on the second semiconductor device layer, second front-surface pads in the second front-surface insulating layer, a second back-surface insulating layer on a back surface of the second semiconductor substrate, second back-surface pads in the second back-surface insulating layer, and a second through-electrode extending through the second semiconductor substrate and electrically connecting the second front-surface pads and the second back-surface pads to each other, wherein the second front-surface insulating layer of a lowermost second semiconductor chip among the plurality of second semiconductor chips is bonded to the first back-surface insulating layer, and the second front-surface pads of the lowermost second semiconductor chip are bonded to the first back-surface pads, respectively.

2 . The semiconductor package of claim 1 , wherein the first back-surface pads have an upper surface coplanar with an upper surface of the first back-surface insulating layer, and the second front-surface pads have an upper surface coplanar with an upper surface of the second front-surface insulating layer.

3 . The semiconductor package of claim 1 , wherein the plurality of second semiconductor chips is stacked in a first direction, and
wherein the metal oxide film of each of the dummy pads has an upper surface higher in the first direction than an upper surface of the first back-surface insulating layer.

4 . The semiconductor package of claim 1 , wherein the metal oxide film includes an oxide containing a metal included in each of the dummy pads.

5 . The semiconductor package of claim 1 , wherein
the first semiconductor chip further includes first back-surface dummy pads on the back surface of the first semiconductor substrate in the first region of the first back-surface insulating layer, and the lowermost second semiconductor chip is on the front surface of the second semiconductor substrate in the second front-surface insulating layer, and further includes second front-surface dummy pads respectively bonded to the first back-surface dummy pads.

6 . The semiconductor package of claim 1 , wherein
the first semiconductor chip further includes at least one alignment key pad on the back surface of the first semiconductor substrate in the second region of the first back-surface insulating layer, and an additional metal oxide film is on the at least one alignment key pad.

7 . The semiconductor package of claim 1 , wherein the metal oxide film is in direct contact with the molded layer.

8 . The semiconductor package of claim 1 , wherein the molded layer includes a monolithic structure formed of a single material.

9 . The semiconductor package of claim 1 , wherein the second back-surface insulating layer of each of the plurality of second semiconductor chips is bonded to a second front-surface insulating layer of another adjacent one of the plurality of second semiconductor chips, and the second back-surface pads of each of the plurality of second semiconductor chips are respectively bonded to second front-surface pads of another adjacent one of the plurality of second semiconductor chips.

10 . The semiconductor package of claim 1 , wherein each of the plurality of second semiconductor chips is a same type of semiconductor chip, which is different from that of the first semiconductor chip.

11 . The semiconductor package of claim 10 , wherein
the first semiconductor chip includes a logic chip, and the plurality of second semiconductor chips includes memory chips, respectively.

12 . The semiconductor package of claim 1 , wherein
a third semiconductor chip on an uppermost second semiconductor chip among the plurality of second semiconductor chips, and the third semiconductor chip includes: a third semiconductor substrate; a third semiconductor device layer on a front surface of the third semiconductor substrate; a third front-surface insulating layer on the third semiconductor device layer and bonded to a second back-surface insulating layer of the uppermost second semiconductor chip; and second front-surface pads in the third front-surface insulating layer and respectively bonded to second back-surface pads of the uppermost second semiconductor chip.

13 . A semiconductor package comprising:
a base structure having an upper surface divided into a first region and a second region, the base structure including a base insulating layer on the upper surface, connection pads bordered by the base insulating layer and arranged on the first region, and dummy pads bordered by the base insulating layer, arranged on the second region, each of the dummy pads having an upper surface on which a metal oxide film is disposed; at least one semiconductor chip on the first region of the base structure, the at least one semiconductor chip including a semiconductor substrate, a semiconductor device layer on a front surface of the semiconductor substrate, a front-surface insulating layer on the semiconductor device layer and bonded to the base insulating layer in the first region, and front-surface pads bordered by the front-surface insulating layer and respectively bonded to the connection pads; and a molded layer on the base structure and bordering side surfaces of the at least one semiconductor chip.

14 . The semiconductor package of claim 13 , wherein an upper surface of the metal oxide film is higher than upper surfaces of the connection pads in a direction perpendicular to a plan defined by the upper surface of the base structure.

15 . The semiconductor package of claim 13 , wherein the metal oxide film has a thickness of about 5 nm to about 80 nm.

16 . The semiconductor package of claim 13 , wherein the base structure includes a substrate having a wiring circuit.

17 . The semiconductor package of claim 13 , wherein the base structure includes a semiconductor chip of a different type from that of the at least one semiconductor chip.

18 . A semiconductor package comprising:
a first semiconductor chip having an upper surface and a lower surface, the upper

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Aenee
• Lee Wonil

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/90 Primary

  Bond pads, in general · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/731

  of die-attach connectors · CPC title