Bonding structure of dies with dangling bonds

Patent metadata

Field	Value
Publication number	US-10861808-B2
Application number	US-201916371863-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Nov 21, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.

First claim

What is claimed is:

1. A method comprising:
polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a plurality of bond pads in the dielectric layer, wherein the plurality of bond pads comprise first active bond pads and first dummy bond pads, wherein the first active bond pads are electrically coupled to the first through-vias; and
bonding the first die to a second die, wherein both of the first active bond pads and the first dummy bond pads are bonded to corresponding bond pads in the second die.

2. The method of claim 1 , wherein the first active bond pads are bonded to a second plurality of active bond pads in the second die, and the first dummy bond pads are bonded to dangling bond pads in the second die, and wherein both the second plurality of active bond pads and the dangling bond pads are electrically connected to integrated circuit devices in the second die.

3. The method of claim 1 , wherein the first die and the second die are bonded through hybrid bonding.

4. The method of claim 1 further comprising bonding a dummy die to the first die.

5. The method of claim 4 , wherein the plurality of bond pads further comprise second dummy bond pads, and the dummy die further comprises third dummy bond pads bonded to the second dummy bond pads.

6. The method of claim 1 further comprising:
disposing a filling dielectric material to encircle the second die;
planarizing the second die and the filling dielectric material, until second through-vias in the second die are exposed; and
forming third active bond pads electrically coupling to the second through-vias.

7. The method of claim 6 , wherein the plurality of bond pads further comprise fourth dummy bond pads, and top surfaces of the fourth dummy bond pads are in contact with the filling dielectric material.

8. The method of claim 1 , wherein the first die is a logic die, and the second die is a memory die.

9. The method of claim 1 further comprising stacking a third die identical to the second die over the second die, wherein no bond pads in the second die and also bonded to the third die are used as dangling bond pads.

10. A method comprising:
forming a first die comprising:
a first semiconductor substrate; and
a first through-via penetrating through the first semiconductor substrate;

forming a second die comprising:
a second semiconductor substrate;
a second through-via penetrating through the second semiconductor substrate;
a first active bond pad; and
a first dangling bond pad; and

bonding the second die over the first die, wherein the first active bond pad is electrically coupled to first die through a second active bond pad between the first die and the second die, and the first dangling bond pad is bonded to a first dummy pad between the first die and the second die.

11. The method of claim 10 further comprising:
placing the first die over a carrier;
encapsulating the first die in a filling dielectric material;
forming a dielectric layer overlapping the first die and the filling dielectric material; and
forming the second active bond pad and the first dangling bond pad in the dielectric layer.

12. The method of claim 10 further comprising:
performing a gap filling process to embed the second die in a gap-filling material, wherein the gap-filling material is over and contacts a top surface of a second dummy pad, with the second dummy pad being between the first die and the second die.

13. The method of claim 10 further comprising:
bonding a dummy die to the first die, wherein the dummy die contacts a third dummy pad between the first die and the second die, and the third dummy pad is at a same level as the second active bond pad and the first dummy pad.

14. The method of claim 13 , wherein the dummy die further comprises a fourth dummy pad bonded to the third dummy pad in the dummy die.

15. The method of claim 10 , wherein before the second die is bonded to the first die, the first dummy pad is electrically floating.

16. The method of claim 10 further comprising:
polishing the first semiconductor substrate to reveal the first through-via;
forming a dielectric layer over and contacting the first semiconductor substrate; and
forming the second active bond pad and the first dummy pad in the dielectric layer, wherein an entire bottom surface of the first dummy pad is in contact with a top surface of an additional dielectric layer in the first die.

17. A method comprising:
forming a dielectric layer on a surface of a semiconductor substrate of a first die;
forming a plurality of bond pads in the dielectric layer, wherein the plurality of bond pads comprise a dummy bond pad;
bonding the first die to a second die, wherein the dummy bond pad is bonded to a dangling bond pad in the second die, and wherein the dangling bond pad in the second die is electrically connected to integrated circuit devices in the second die;
embedding the second die in a dielectric material;
planarizing the second die and the dielectric material, until through-vias in the second die are exposed; and
forming active bond pads electrically coupling to the through-vias.

18. The method of claim 17 , wherein the first die and the second die are bonded through hybrid bonding.

19. The method of claim 17 , wherein the first die is a logic die, and the second die is a memory die.

20. The method of claim 17 , wherein before the second die is bonded to the first die, the dummy bond pad is electrically floating.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chen Ming-Fa
• Hu Chih-Chia

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/411

  Chip-supporting parts, e.g. die pads · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title