Method of fabricating semiconductor device including organic and silicon oxide layers

Patent metadata

Field	Value
Publication number	US-12588478-B2
Application number	US-202318312811-A
Country	US
Kind code	B2
Filing date	May 5, 2023
Priority date	Aug 31, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A method of fabricating a semiconductor device includes forming a first layer which has a first surface, does not contain an acid, and contains a metal material. The method includes forming, on the first layer, a second layer which includes a trench exposing the first surface. The second layer has a second surface intersecting the first surface within the trench, and contains an acid and an organic material. The method further including a first precursor containing an alkoxy group and silicon; and forming a third layer containing silicon oxide on the second surface within the trench. The third layer is in contact with a portion of the first surface within the trench.

First claim

What is claimed:

1 . A method of fabricating a semiconductor device, comprising:
forming a first layer which has a first surface, does not comprise an acid, and comprises a metal material; forming, on the first layer, a second layer which defines a trench exposing the first surface, has a second surface intersecting the first surface within the trench, and comprises an acid and an organic material; providing a first precursor comprising an alkoxy group and silicon; and forming a third layer comprising silicon oxide on the second surface within the trench, wherein the third layer is in contact with a portion of the first surface within the trench.

2 . The method of claim 1 , wherein the forming of the third layer is performed at a temperature of 130° C. or higher and 250° C. or lower.

3 . The method of claim 1 , further comprising:
providing a second precursor comprising an amine before forming the third layer.

4 . The method of claim 3 , wherein the second layer does not comprise an amine.

5 . The method of claim 3 , wherein
the forming of the third layer comprises forming a fourth layer comprising a silanol on the first surface, and the second precursor comprises Si—N bonds.

6 . The method of claim 5 , wherein a thickness of the fourth layer is less than a thickness of the third layer.

7 . The method of claim 1 , wherein the first surface comprises a first portion in contact with the third layer and a second portion not in contact with the third layer.

8 . The method of claim 1 , wherein the second layer comprises an amine.

9 . The method of claim 8 , wherein the first precursor does not comprise an amine.

10 . The method of claim 1 , wherein the first precursor comprises any one of tetramethyl orthosilicate, tetraethyl orthosilicate, (3-Aminopropyl) trimethoxysilane, (3-Aminopropyl) triethoxysilane, (3-mercaptopropyl) trimethoxysilane, tetramethylsilanediamine, and (3-mercaptopropyl) triethoxysilane.

11 . A method of fabricating a semiconductor device, comprising:
forming, on a titanium nitride layer, an organic layer comprising an acid-precursor and an amine; forming a trench that exposes the titanium nitride layer by etching the organic layer; providing a first precursor comprising an alkoxy group and silicon; and forming a silicon oxide layer on the organic layer, wherein the forming of the silicon oxide layer comprises forming a first material comprising a silanol by using hydrogen ions produced from the organic layer and the first precursor and forming a second material comprising siloxane using the first material and the amine of the organic layer.

12 . The method of claim 11 , wherein the forming of the silicon oxide layer is performed at a temperature of 130° C. or higher and 250° C. or lower.

13 . The method of claim 11 , wherein the silicon oxide layer is in contact with a portion of the titanium nitride layer within the trench and the titanium nitride layer is exposed between the silicon oxide es layer within the trench.

14 . The method of claim 11 , further comprising:
providing a second precursor comprising an amine before forming the silicon oxide layer.

15 . The method of claim 14 , wherein the second precursor further comprises silicon.

16 . The method of claim 14 , further comprising:
forming a sub-film comprising a silanol on the titanium nitride layer, wherein the second precursor comprises Si—N bonds and a thickness of the sub-film is less than a thickness of the silicon oxide layer.

17 . The method of claim 14 , further comprising:
providing a third precursor comprising an amine before forming the silicon oxide layer, wherein the second precursor does not comprise Si—N bonds and the third precursor comprises Si—N bonds.

18 . A method of fabricating a semiconductor device, comprising:
providing a substrate comprising a first region and a second region; forming a first sheet pattern on the substrate in the first region; forming a second sheet pattern on the substrate in the second region; forming, on the substrate, a work function metal layer surrounding the first sheet pattern and the second sheet pattern; forming, on the substrate, a sacrificial layer covering the first sheet pattern and the second sheet pattern and comprising an acid-precursor and an amine; forming, between the first sheet pattern and the second sheet pattern, a trench penetrating the sacrificial layer, the trench exposing the work function metal layer; and forming, on the sacrificial layer, a protective film comprising silicon oxide, wherein the protective film covers a surface of the sacrificial layer and the work function metal layer is exposed between the protective film within the trench.

19 . The method of claim 18 , further comprising:
removing the work function metal layer exposed between the protective film within the trench.

20 . The method of claim 18 , wherein an NMOS is formed on the substrate in the first region and a PMOS is formed on the substrate in the second region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Eun Hyea
• Han Hoon
• Hwang Byung Keun
• Sung Young Hun
• Cho Youn Joung

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title