Gate-all-around (GAA) method and devices

Patent metadata

Field	Value
Publication number	US-11101359-B2
Application number	US-201916409386-A
Country	US
Kind code	B2
Filing date	May 10, 2019
Priority date	Nov 28, 2018
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

First claim

What is claimed is:

1. A method of manufacturing a device, comprising:
forming a first stack of alternating layers on a substrate, wherein forming the first stack of alternating layers comprises depositing alternating first layers of a first semiconductor material and second layers of a second semiconductor material different from the first semiconductor material on the substrate;
forming a second stack of alternating layers on the substrate at a first distance from the first stack of alternating layers, wherein forming the second stack of alternating layers comprises conformally depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material within a recess formed in the first stack of alternating layers on the substrate, wherein the first layers of the second stack of alternating layers have a thickness greater than the first layers of the first stack of alternating layers, and wherein at least one deposited first layer of the first semiconductor material of the second stack extends to the top of a sidewall of the recess;
constructing a first stack of nanosheets from the first stack of alternating layers and a second stack of nanosheets from the second stack of alternating layers, wherein the constructing the first and second stack of nanosheets comprises:
patterning a first fin from the first stack of alternating layers and a second fin from the second stack of alternating layers; and
removing the first layers from the first stack of alternating layers and removing the first layers from the second stack of alternating layers, such that the distances between adjacent remaining layers of the second stack of alternating layers are greater than the distances between adjacent remaining layers of the first stack of alternating layers; and

forming a first gate dielectric over the first stack of nanosheets and a second gate dielectric over the second stack of nanosheets.

2. The method of claim 1 , wherein the first gate dielectric is formed to comprise a first gate dielectric thickness and the second gate dielectric is formed to comprise a second gate dielectric thickness greater than the first gate dielectric thickness.

3. The method of claim 1 , wherein the first and second gate dielectrics are formed to comprise different materials.

4. The method of claim 1 , wherein the first stack of alternating layers is formed to comprise a first number of alternating layers by controlling the number of cycles of epitaxial growth used to form the first stack of alternating layers, wherein the second stack of alternating layers is formed to comprise a second number of alternating layers by controlling the number of cycles of epitaxial growth used to form the second stack of alternating layers, and wherein the first number is different from the second number.

5. The method of claim 1 , wherein the second layers of the second stack of alternating layers are formed to have a thickness greater than the second layers of the first stack of alternating layers.

6. A method of manufacturing a device, comprising:
etching a recess in a first stack of alternating layers, wherein the first stack of alternating layers comprises alternating first layers comprising a first semiconductor material and second layers comprising a second semiconductor material different from the first semiconductor material on a substrate, wherein the first layers of the first stack of alternating layers have a first average thickness and the second layers of the first stack of alternating layers have a second average thickness, wherein the first average thickness and the second average thickness are determined by controlling epitaxial growth of the first and second layers of the first stack of alternating layers;
forming a spacer on sidewalls of the recess;
forming a second stack of alternating layers within the first stack of alternating layers, wherein the forming the second stack of alternating layers comprises depositing alternating first layers comprising the first semiconductor material and second layers comprising the second semiconductor material in the recess between sidewalls of the spacer, wherein the first layers of the second stack of alternating layers have a third average thickness and the second layers of the second stack of alternating layers have a fourth average thickness, wherein the third average thickness is different from the first average thickness and wherein the fourth average thickness is different from the second average thickness, wherein the third average thickness and the fourth average thickness are determined by controlling epitaxial growth of the first and second layers of the second stack of alternating layers;
constructing a first stack of nanosheets from the first stack of alternating layers and a second stack of nanosheets from the second stack of alternating layers, wherein constructing the first and second stack of nanosheets comprises:
patterning a first fin from the first stack of alternating layers and a second fin from the second stack of alternating layers; and
removing one out of the first layers and the second layers from the first stack of alternating layers and the second stack of alternating layers; and

forming a first gate dielectric over the first stack of nanosheets and a second gate dielectric over the second stack of nanosheets.

7. The method of claim 6 , wherein the first stack of nanosheets is formed to have a first width, the second stack of nanosheets is formed to have a second width, and the first width is different from the second width.

8. The method of claim 6 , wherein the first and second stacks of nanosheets are formed to comprise different numbers of nanosheets.

9. The method of claim 6 , wherein patterning the second fin comprises etching away the spacer.

10. The method of claim 6 , wherein forming a second stack of alternating layers further comprises depositing alternating first layers of the first semiconductor material and second layers of the second semiconductor material conformally on a bottom and sidewalls of the recess.

11. The method of claim 10 , wherein patterning the second fin comprises etching away an outer portion of the second stack of alternating layers such that the remaining portion comprises only alternating horizontal first layers of the first semiconductor material and horizontal second layers of the second semiconductor material.

12. A method of manufacturing a device, comprising:
depositing on a substrate alternating first layers of a first semiconductor material and second layers of a second semiconductor material different from the first semiconductor material;
patterning the alternating first layers and second layers to form a trench therein;
lining the trench sidewalls and bottom with a spacer;
depositing within the lined trench alternating third layers of the first semiconductor material and fourth layers of the second semiconductor material on the substrate, wherein the third layers have a thickness greater than the first layers;
patterning the alternating first layers and second layers to form a first fin;
patterning the alternating third layers and fourth layers to form a second fin;
at least partially removing the first layers from the first fin and at least partially removing the third layers from the second fin;
forming a first gate dielectric over the patterned second layers; and
forming a second gate dielectric over patterned fourth layers.

13. The method of claim 12 , wherein the step of patterning the alternating third layers and fourth layers to form a second fin comprises etching away an outer portion of the alternating thi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Shien-Yang
• Lin Ta-Chun
• Pan Kuo-Hua

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title