Stacked electronic devices having independent gates

Patent metadata

Field	Value
Publication number	US-12588273-B2
Application number	US-202318191895-A
Country	US
Kind code	B2
Filing date	Mar 29, 2023
Priority date	Mar 29, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
a stacked device configuration comprising a top electronic device positioned over a bottom electronic device; an isolation region between the top electronic device and the bottom electronic device; and a first gate contact structure electrically coupled to a gate region of the top electronic device; wherein a bottom surface of the first gate contact structure is on a portion of the isolation region; wherein the gate region of the top electronic device comprises a top gate dielectric layer; and wherein the first gate contact structure extends through the top gate dielectric layer to allow the bottom surface of the first gate contact structure to be on the portion of the isolation region.

2 . The IC of claim 1 , wherein:
the gate region of the top electronic device comprises a first conductive material; the gate region of the bottom electronic device comprises a second conductive material; and a work function of the first conductive material is different from a work function of the second conductive material.

3 . The IC of claim 2 , wherein:
the top electronic device comprises a p-type transistor; and the bottom electronic device comprises an n-type transistor.

4 . The IC of claim 2 , wherein:
the top electronic device comprises an n-type transistor; and the bottom electronic device comprises a p-type transistor.

5 . The IC of claim 2 , wherein:
the top electronic device comprises a memory device operable to perform storage operations; and the bottom electronic device comprises a transistor operable to perform logic operations.

6 . The IC of claim 1 , wherein a portion of the first gate contact structure is electrically coupled to the gate region of the top electronic device through a sidewall of the gate region of the top electronic device.

7 . The IC of claim 6 , wherein the first gate contact structure is electronically isolated except for the portion of the first gate contact structure that is electrically coupled through the sidewall of the gate region of the top electronic device.

8 . The IC of claim 2 , wherein the second conductive material is different from the first conductive material.

9 . The IC of claim 1 , wherein the isolation region is operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device.

10 . The IC of claim 6 , wherein a second gate contact structure:
extends through the gate region of the top electronic device; is electrically coupled to a gate region of the bottom electronic device through a top surface of the gate region of the bottom electronic device; and is electrically isolated from the gate region of the top electronic device.

11 . A method of fabricating an integrated circuit (IC), the method comprising:
forming a stacked device configuration comprising a top electronic device positioned over a bottom electronic device; forming an isolation region between the top electronic device and the bottom electronic device; and forming a first gate contact structure electrically coupled to a gate region of the top electronic device; wherein a bottom surface of the first gate contact structure is on a portion of the isolation region; wherein the gate region of the top electronic device comprises a top gate dielectric layer; and wherein the first gate contact structure extends through the top gate dielectric layer to allow the bottom surface of the first gate contact structure to be on the portion of the isolation region.

12 . The method of claim 11 , wherein:
the gate region of the top electronic device comprises a first conductive material; the gate region of the bottom electronic device comprises a second conductive material; and a work function of the first conductive material is different from a work function of the second conductive material.

13 . The method of claim 12 , wherein:
the top electronic device comprises a p-type transistor; and the bottom electronic device comprises an n-type transistor.

14 . The method of claim 12 , wherein:
the top electronic device comprises an n-type transistor; and the bottom electronic device comprises a p-type transistor.

15 . The method of claim 12 , wherein:
the top electronic device comprises a memory device operable to perform storage operations; and the bottom electronic device comprises a transistor operable to perform logic operations.

16 . The method of claim 11 further comprising electrically coupling a portion of the first gate contact structure to the gate region of the top electronic device through a sidewall of the gate region of the top electronic device.

17 . The method of claim 16 further comprising electronically isolating the first gate contact structure except for the portion of the first gate contact structure that is electrically coupled through the sidewall of the gate region of the top electronic device.

18 . The method of claim 12 , wherein the second conductive material is different from the first conductive material.

19 . The method of claim 18 , wherein the isolation region is operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device.

20 . The method of claim 16 further comprising:
forming a second gate contact structure that extends through the gate region of the top electronic device;
electrically coupling the second gate contact structure to a gate region of the bottom electronic device through a top surface of the gate region of the bottom electronic device; and
electrically isolating the second gate contact structure from the gate region of the top electronic device.

Assignees

• IBM

Inventors

• Sung Min Gyu
• Xie Ruilong
• Frougier Julien
• Park Chanro
• Li Juntao

Classifications

• H10D84/852

  comprising forksheet IGFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D89/217

  comprising arrangements for charge injection in static induction transistor logic [SITL] devices · CPC title

• H10D48/366 Primary

  Multistable devices; Devices having two or more distinct operating states · CPC title

• H10D88/01

  Manufacture or treatment · CPC title