Gate-cut and separation techniques for enabling independent gate control of stacked transistors

Patent metadata

Field	Value
Publication number	US-12336294-B2
Application number	US-202117522974-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Nov 10, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

First claim

What is claimed is:

1. A device comprising:
vertically stacked transistors comprising at least one first transistor and at least one second transistor separated by a dielectric isolation layer; and
gate material adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material, the gate material being positioned on an underlayer;
wherein one end of the dielectric isolation layer is adjacent to the at least one second height vertical layer and another end is adjacent to another vertical layer, the another vertical layer comprising a top surface and a bottom surface;
wherein the top surface of the another vertical layer abuts a conductive portion of the gate material and the bottom surface abuts the underlayer.

2. The device of claim 1 , wherein the at least one second height vertical layer abuts the dielectric isolation layer.

3. The device of claim 1 , wherein the at least one second height vertical layer is adjacent to the dielectric isolation layer so as to electrically isolate the at least one first transistor from the at least one second transistor.

4. The device of claim 1 , wherein the at least one second height vertical layer is about half the height of the gate material.

5. The device of claim 1 , wherein an arrangement of the at least one first height vertical layer and the dielectric isolation layer provides independent control of the gate material for the at least one first transistor and the at least one second transistor.

6. The device of claim 1 , wherein an arrangement of the at least one first height vertical layer and the dielectric isolation layer provides shared control of the gate material for the at least one first transistor and the at least one second transistor.

Assignees

• IBM

Inventors

• Xie Ruilong
• Loubet Nicolas
• Frougier Julien
• Clevenger Lawrence A
• Bhosale Prasad
• Wang Junli
• Pranatharthiharan Balasubramanian
• Guo Dechao

Classifications

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title