Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs

Patent metadata

Field	Value
Publication number	US-11522048-B2
Application number	US-201916361861-A
Country	US
Kind code	B2
Filing date	Mar 22, 2019
Priority date	Mar 22, 2019
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires;
a first gate stack around the first vertical arrangement of horizontal nanowires, and a second gate stack around the second vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, the first pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires;
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, the second pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires, wherein one of the first pair of epitaxial source or drain structures is laterally adjacent to but not merged with one of the second pair of epitaxial source or drain structures; and
a conductive contact structure laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures, wherein the conductive contact is continuous vertically between vertically adjacent ones of the vertically discrete portions of the first pair of epitaxial source or drain structures, and the conductive contact is continuous vertically between vertically adjacent ones of the vertically discrete portions of the second pair of epitaxial source or drain structures.

2. The integrated circuit structure of claim 1 , wherein the conductive contact structure surrounds the vertically discrete portions of the first pair of epitaxial source or drain structures and surrounds the vertically discrete portions of the second pair of epitaxial source or drain structures.

3. The integrated circuit structure of claim 1 , further comprising:
a first sub-fin structure beneath the first vertical arrangement of horizontal nanowires; and
a second sub-fin structure beneath the second vertical arrangement of horizontal nanowires.

4. The integrated circuit structure of claim 1 , wherein one of the first and second pairs of epitaxial source or drain structures is a pair of compressive-stressing source or drain structures.

5. The integrated circuit structure of claim 1 , wherein one of the first and second pairs of epitaxial source or drain structures is a pair of tensile-stressing source or drain structures.

6. The integrated circuit structure of claim 1 , wherein one of the first and second gate stacks comprises a high-k gate dielectric layer and a metal gate electrode.

7. A method of fabricating an integrated circuit structure, the method comprising:
forming a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires;
forming a first dummy gate stack over the first vertical arrangement of horizontal nanowires, and a second dummy gate stack over the second vertical arrangement of horizontal nanowires;
forming a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, the first pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires;
forming a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, the second pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires, wherein one of the first pair of epitaxial source or drain structures is laterally adjacent to but not merged with one of the second pair of epitaxial source or drain structures;
forming a dummy contact structure between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures;
subsequent to forming the dummy contact structure, replacing the first and second dummy gate stacks with first and second permanent gate stacks, respectively;
subsequent to replacing the first and second dummy gate stacks with the first and second permanent gate stacks, removing the dummy contact structure; and
forming a conductive contact structure laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures, wherein the conductive contact is continuous vertically between vertically adjacent ones of the vertically discrete portions of the first pair of epitaxial source or drain structures, and the conductive contact is continuous vertically between vertically adjacent ones of the vertically discrete portions of the second pair of epitaxial source or drain structures.

8. The method of claim 7 , wherein the conductive contact structure surrounds the vertically discrete portions of the first pair of epitaxial source or drain structures and surrounds the vertically discrete portions of the second pair of epitaxial source or drain structures.

9. The method of claim 7 , wherein one of the first and second pairs of epitaxial source or drain structures is a pair of compressive-stressing source or drain structures.

10. The method of claim 7 , wherein one of the first and second pairs of epitaxial source or drain structures is a pair of tensile-stressing source or drain structures.

11. The method of claim 7 , wherein one of the first and second gate permanent stacks comprises a high-k gate dielectric layer and a metal gate electrode.

12. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires;
a first gate stack around the first vertical arrangement of horizontal nanowires, and a second gate stack around the second vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, the first pair of epitaxial source or drain structures comprising vertically non-discrete portions aligned with the first vertical arrangement of horizontal nanowires;
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, the second pair of epitaxial source or drain structures comprising vertically non-discrete portions aligned with the second vertical arrangement of horizontal nanowires, wherein one of the first pair of epitaxial source or drain structures is laterally adjacent to but not merged with one of the second pair of epitaxial source or drain structures; and
a conductive contact structure laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

13. The integrated circuit structure of claim 12 , further comprising:
a first sub-fin structure beneath the first vertical arrangement of horizontal nanowires; and
a second sub-fin structure beneath the second vertical arrangement of horizontal nanowires.

14. The integrated circuit structure of claim 12 , wherein one of the first and second pairs of epitaxial source or drain structures is a pair of compressive-stressing source or drain structures.

Assignees

• Intel Corp

Inventors

• Bomberger Cory
• Murthy Anand
• Bohr Mark T
• Ghani Tahir
• Guha Biswajeet

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic