Multi-layer electrode to improve performance of ferroelectric memory device

Patent metadata

Field	Value
Publication number	US-12588271-B2
Application number	US-202318366787-A
Country	US
Kind code	B2
Filing date	Aug 8, 2023
Priority date	Jun 16, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

First claim

What is claimed is:

1 . A memory device, comprising:
a first bottom electrode layer overlying a substrate, wherein the first bottom electrode layer comprises a first non-oxide conductive material; a ferroelectric switching layer disposed over the first bottom electrode layer; a first top electrode layer disposed over the ferroelectric switching layer; and a second bottom electrode layer disposed between the first bottom electrode layer and the ferroelectric switching layer, wherein the second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer, wherein the second bottom electrode layer contacts a bottom surface of the ferroelectric switching layer and comprises a second non-oxide conductive material different from the first non-oxide conductive material.

2 . The memory device of claim 1 , wherein the first non-oxide conductive material comprises a first metal and the second non-oxide conductive material comprises a second metal different from the first metal.

3 . The memory device of claim 1 , wherein the first non-oxide conductive material utilizes a first Gibbs free energy to form an oxide and the second non-oxide conductive material utilizes a second Gibbs free energy to form an oxide that is greater than the first Gibbs free energy.

4 . The memory device of claim 1 , wherein the first non-oxide conductive material comprises titanium nitride or tantalum nitride, and the second non-oxide conductive material comprises ruthenium, platinum, iridium, gold, palladium, osmium, molybdenum, or tungsten.

5 . The memory device of claim 1 , further comprising:
a second top electrode layer disposed between the first top electrode layer and the ferroelectric switching layer, wherein the second top electrode layer is less susceptible to oxidation than the first top electrode layer.

6 . The memory device of claim 5 , wherein the first top electrode layer comprises the first non-oxide conductive material, wherein the second top electrode layer comprises the second non-oxide conductive material.

7 . The memory device of claim 5 , wherein sidewalls of the first bottom electrode layer, sidewalls of the second bottom electrode layer, and sidewalls of the ferroelectric switching layer are aligned.

8 . The memory device of claim 7 , wherein sidewalls of the first top electrode layer and sidewalls of the second top electrode layer are aligned and spaced laterally between the sidewalls of the ferroelectric switching layer.

9 . The memory device of claim 1 , wherein the second bottom electrode layer has a corrosion potential of greater than approximately-0.75V.

10 . An integrated chip, comprising:
a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate; a memory cell disposed over the lower interconnect, wherein the memory cell comprises a ferroelectric switching layer disposed between a multi-layer bottom electrode and a multi-layer top electrode; and wherein the multi-layer bottom electrode comprises a first bottom electrode layer and a second bottom electrode layer disposed between the first bottom electrode layer and the ferroelectric switching layer, wherein the multi-layer top electrode comprises a first top electrode layer and a second top electrode layer disposed between the first top electrode layer and the ferroelectric switching layer, wherein the first bottom electrode layer and the first top electrode layer comprise a first material and the second bottom electrode layer and the second top electrode layer comprise a second material different than the first material, wherein the second bottom electrode layer and the second top electrode layer are respectively configured to prevent oxidation of the first bottom electrode layer and the first top electrode layer.

11 . The integrated chip of claim 10 , wherein the first material has a first corrosion potential and the second material has a second corrosion potential greater than the first corrosion potential, wherein the first material and the second material are each a non-oxide.

12 . The integrated chip of claim 10 , wherein the second bottom electrode layer directly contacts a lower surface of the ferroelectric switching layer and the second top electrode layer directly contacts an upper surface of the ferroelectric switching layer.

13 . The integrated chip of claim 12 , further comprising:
a lower insulating structure disposed over the lower ILD layer; and wherein the first bottom electrode layer continuously extends along an upper surface of the lower insulating structure, along opposing sidewalls of the lower insulating structure, to an upper surface of the lower interconnect.

14 . The integrated chip of claim 13 , wherein the second top electrode layer comprises a middle region overlying the lower interconnect and a peripheral region overlying the upper surface of the ferroelectric switching layer, wherein a lower surface of the middle region is vertically below the upper surface of the lower insulating structure.

15 . The integrated chip of claim 10 , wherein outer sidewalls of the multi-layer top electrode are spaced laterally between outer sidewalls of the ferroelectric switching layer.

16 . The integrated chip of claim 10 , further comprising:
a hard mask layer disposed over the memory cell, wherein the hard mask layer continuously extends from an upper surface of the ferroelectric switching layer, along a sidewall of the second top electrode layer, to an upper surface of the first top electrode layer.

17 . An integrated chip, comprising:
a lower interconnect over a substrate; a lower insulating structure over the lower interconnect; a multi-layer bottom electrode over the lower interconnect and comprising a first bottom electrode layer stacked with a second bottom electrode layer, wherein the multi-layer bottom electrode comprises a central region extending through the lower insulating structure to contact the lower interconnect and an outer region disposed on a top surface of the lower insulating structure; a ferroelectric layer on the multi-layer bottom electrode; and a multi-layer top electrode on the ferroelectric layer, wherein a bottom surface of the multi-layer top electrode is below the top surface of the lower insulating structure, wherein the multi-layer top electrode comprises a first top electrode layer stacked with a second top electrode layer, wherein a first Gibbs free energy of the first top and bottom electrode layers is less than a second Gibbs free energy of the second top and bottom electrode layers.

18 . The integrated chip of claim 17 , wherein the second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric layer, wherein the second top electrode layer is disposed between the first top electrode layer and the ferroelectric layer.

19 . The integrated chip of claim 17 , wherein the second bottom electrode layer is configured to prevent oxidation of the first bottom electrode layer during a baking process.

20 . The integrated chip of claim 17 , wherein a thickness of the ferroelectric layer is greater than a thickness of the second bottom electrode layer and a thickness of the second top electrode layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wei Yi Yang
• Lee Bi-Shen
• Lai Hsin-Yu
• Trinh Hai-Dang
• Lin Hsing-Lien
• Kuang Hsun-Chung

Classifications

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/688

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10B53/00

  Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors · CPC title