Semiconductor devices including separation structure

Patent metadata

Field	Value
Publication number	US-12588269-B2
Application number	US-202117388584-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Jan 8, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A semiconductor device includes a plurality of active regions on a substrate. A gate electrode is on, and intersects, the active regions. A plurality of source/drain regions are on the active regions, such that the source/drain regions are adjacent to opposite sides of the gate electrode and the gate electrode is between the source/drain regions. A separation structure is between adjacent source/drain regions. The separation structure includes an insulating pattern and a spacer layer. The insulating pattern includes first and second side surfaces that are opposite side surfaces of the insulating pattern and are adjacent to separate, respective source/drain regions. The spacer layer is on the first and second side surfaces. An uppermost end of the insulating pattern is farther from a lower surface of the substrate than a first upper surface of the spacer layer that is adjacent to the first and second side surfaces.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of active regions on a substrate; a gate electrode intersecting the plurality of active regions; a plurality of source/drain regions on the plurality of active regions, such that the plurality of source/drain regions are adjacent to opposite sides of the gate electrode and the gate electrode is between the plurality of source/drain regions; and a plurality of separation structures, each separate separation structure of the plurality of separation structures between proximate source/drain regions of the plurality of source/drain regions, wherein each separation structure of the plurality of separation structures includes
an insulating pattern that includes a first side surface and a second side surface that are opposite side surfaces of the insulating pattern and are adjacent to separate, respective source/drain regions of the proximate source/drain regions, and
a spacer layer on the first side surface and the second side surface, and the spacer layer at least partially between the insulating pattern and the separate, respective source/drain regions,
wherein an uppermost end of the insulating pattern is farther from a lower surface of the substrate than a first upper surface of the spacer layer that is proximate to the first side surface and the second side surface, wherein the first side surface and the second side surface of the insulating pattern each include
a lower portion contacting the spacer layer,
a middle portion contacting the respective source/drain regions of the proximate source/drain regions, and
an upper portion spaced apart from the respective source/drain regions of the proximate source/drain regions,
wherein a lower surface of the spacer layer is further from the lower surface of the substrate than a central portion of a lower surface of the respective source/drain regions of the proximate source/drain regions, wherein the spacer layer includes
a first spacer layer, and
a second spacer layer between the first spacer layer and the insulating pattern,
wherein each of an upper surface of the first spacer layer and an upper surface of the second spacer layer that is proximate to the first side surface of the insulating pattern and the second side surface of the insulating pattern vertically overlaps and entirely contacts an outer portion of the respective source/drain regions of the proximate source/drain regions, and wherein the upper surface of the second spacer layer is closer to the lower surface of the substrate than the upper surface of the first spacer layer.

2 . The semiconductor device according to claim 1 , wherein the uppermost end of the insulating pattern is at a higher level than a center of each of the plurality of source/drain regions.

3 . The semiconductor device according to claim 1 , wherein
each of the plurality of source/drain regions may have a varying width, and the uppermost end of the insulating pattern is at a higher level than a portion having a maximum horizontal width from among portions of each of the plurality of source/drain regions.

4 . The semiconductor device according to claim 1 , wherein a portion of each of the plurality of source/drain regions directly contact the first side surface and the second side surface.

5 . The semiconductor device according to claim 1 , wherein a distance between the first upper surface of the spacer layer and the uppermost end of the insulating pattern is about 10 nm to about 50 nm.

6 . The semiconductor device according to claim 1 , wherein: the upper surface of the first spacer layer includes an inclined upper surface; and the inclined upper surface has an inclination descending as the inclined upper surface becomes farther from the insulating pattern.

7 . The semiconductor device according to claim 1 , wherein:
the insulating pattern comprises silicon nitride; and the spacer layer comprises silicon oxycarbonitride (SiOCN).

8 . The semiconductor device according to claim 1 , wherein the spacer layer surrounds a lower surface of the insulating pattern.

9 . The semiconductor device according to claim 1 , wherein:
the second spacer layer comprises a material different from a material of the first spacer layer.

10 . The semiconductor device according to claim 1 , wherein:
the first spacer layer comprises silicon oxycarbonitride (SiOCN); the second spacer layer comprises silicon oxide; and the insulating pattern comprises silicon nitride.

11 . The semiconductor device according to claim 1 , wherein
the insulating pattern further comprises a third side surface facing the gate electrode; and the spacer layer extends between the insulating pattern and the gate electrode.

12 . The semiconductor device according to claim 11 , wherein the uppermost end of the insulating pattern is nearer to the lower surface of the substrate than a second upper surface of the spacer layer that is adjacent to the third side surface.

13 . The semiconductor device according to claim 1 , wherein:
each of the plurality of active regions comprises a plurality of active patterns contacting the plurality of source/drain regions; and the gate electrode covers upper and side surfaces of the plurality of active patterns.

14 . The semiconductor device according to claim 13 , wherein the gate electrode surrounds upper, lower and side surfaces of at least one of the plurality of active patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Ha Daewon

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title