Enhanced field resistive RAM integrated with nanosheet technology

Patent metadata

Field	Value
Publication number	US-10770461-B2
Application number	US-201916675935-A
Country	US
Kind code	B2
Filing date	Nov 6, 2019
Priority date	Apr 23, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
providing a fin structure comprising a vertical stack of alternating layers of a sacrificial semiconductor material layer and a semiconductor channel material layer located on a surface of a semiconductor substrate, and a first sacrificial gate structure and a second sacrificial gate structure located on different portions of the fin structure.
forming a first mask partially covering the second sacrificial gate structure;
etching physically exposed portions of the fin structure to provide a nanosheet stack comprised of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet beneath the first sacrificial gate structure, and a material stack of alternating layers of a sacrificial semiconductor material layer portion and a semiconductor channel material layer portion beneath the second sacrificial gate structure and the first mask;
recessing each sacrificial semiconductor material nanosheet of the nanosheet stack and each sacrificial semiconductor material layer portion of the material stack;
forming an inner spacer within a gap formed by the recessing;
forming a second mask protecting the first sacrificial gate structure, the nanosheet stack, the inner spacers formed within the gap formed by recessing the sacrificial semiconductor material nanosheets of the nanosheet stack;
recessing the semiconductor channel material layer portions of the material stack;
removing the second mask;
forming a source/drain (S/D) region on physically exposed sidewalls of each semiconductor channel material nanosheet of the nanosheet stack and a S/D region on a physically exposed sidewall of each recessed semiconductor channel material layer portion of the material stack;
removing the first mask;
removing the first and second sacrificial gate structures, each recessed sacrificial semiconductor material nanosheet and a portion of each recessed sacrificial semiconductor material layer portion; and
forming a first functional gate structure wrapping around each suspended semiconductor channel material nanosheet, and a second functional gate structure on exposed surfaces of each recessed semiconductor channel material layer portion of the material stack.

2. The method of claim 1 , further comprising forming, after the removing of the second mask, an interlayer dielectric (IlD) material surrounding the first and second sacrificial gate structures.

3. The method of claim 2 , further comprising forming, after the forming of the first and second functional gate structures, an additional ILD material onto the ILD material and the first and second functional gate structures.

4. The method of claim 3 , further comprising forming, in any order, a source/drain contact structure directly contacting each S/D region, a first gate contact structure directly contacting the first gate structure, a second gate contact structure directly contacting the second gate structure, and a dummy gate contact structure directly contacting a topmost recessed semiconductor channel material layer portion of the material stack.

5. The method of claim 1 , wherein the forming of the S/D regions comprises an epitaxial growth process.

6. The method of claim 1 , further comprising performing a diffusion anneal to out-diffuse dopant from the S/D regions and into a portion of each of the semiconductor channel material nanosheets and each of the recessed semiconductor channel material layer portions.

7. The method of claim 1 , wherein each of the recessed semiconductor channel material layer portions has a width that is greater than a width of each of the sacrificial semiconductor material layer portions.

8. The method of claim 1 , wherein the second functional gate structure located on the exposed surfaces of each of the recessed semiconductor channel material layer portions of the material stack constituents a resistive memory device.

9. The method of claim 8 , wherein the recessed semiconductor channel material layer portions have sharp corners that facilitate electroforming of a filament of the resistive memory device.

10. The method of claim 1 , wherein each sacrificial semiconductor material is composed of a silicon germanium alloy, and each semiconductor channel material layer is composed of silicon or a III-V compound semiconductor.

11. The method of claim 1 , wherein the providing of the fin structure comprises:
epitaxially growing a semiconductor material stack of the alternating layers of the semiconductor material layer and the semiconductor channel material layer; and
patterning the semiconductor material stack.

12. The method of claim 1 , further comprising forming a gate spacer on a sidewall of the first and second sacrificial gate structures, wherein the gate spacer straddles over the fin structure.

13. The method of claim 1 , wherein the recessing of each sacrificial semiconductor material sheet of the nanosheet stack and each sacrificial semiconductor layer portion of the material stack comprises a lateral etch.

14. The method of claim 13 , wherein the lateral etch occurs inward from both sidewalls of each sacrificial semiconductor material sheet of the nanosheet stack, and wherein the lateral etch only occurs from a sidewall of each sacrificial semiconductor material layer portion that faces the first sacrificial gate structure.

15. The method of claim 1 , wherein the recessing of semiconductor channel material layers portions of the material stack forms a gap located above and below each recessed sacrificial semiconductor material layer portion, wherein the gap is located only on one side of the material stack that faces the first sacrificial gate structure.

16. The method of claim 1 , wherein the S/D region that is formed on the sidewall of each of the semiconductor channel material layer portions of the material stack is located on a side of the material stack facing the first sacrificial gate structure.

17. The method of claim 4 , wherein each source/drain contact structure, each gate contact structure and the dummy contact structure have a topmost surface that is coplanar with each other.

18. A method of forming a semiconductor structure, the method comprising:
providing a fin structure comprising a vertical stack of alternating layers of a sacrificial semiconductor material layer and a semiconductor channel material layer located on a surface of a semiconductor substrate, and a first sacrificial gate structure and a second sacrificial gate structure located on different portions of the fin structure.
forming a first mask partially covering the second sacrificial gate structure;
etching physically exposed portions of the fin structure to provide a nanosheet stack comprised of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet beneath the first sacrificial gate structure, and a material stack of alternating layers of a sacrificial semiconductor material layer portion and a semiconductor channel material layer portion beneath the second sacrificial gate structure and the first mask;
recessing each sacrificial semiconductor material nanosheet of the nanosheet stack and each sacrificial semiconductor material layer portion of the material stack;
forming an inner spacer within a gap formed by the recessing;
forming a second mask protecting the first sacrificial gate structure, the nanosheet stack, the inner spacers formed within the gap formed by recessing the sacrificial

Assignees

• IBM

Inventors

• Hashemi Pouya
• Ando Takashi
• Reznicek Alexander

Classifications

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title