Discrete three-dimensional processor

Patent metadata

Field	Value
Publication number	US-12582006-B2
Application number	US-202318117472-A
Country	US
Kind code	B2
Filing date	Mar 5, 2023
Priority date	Dec 10, 2018
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises memory arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the memory arrays. The first and second dice have substantially different structures, more particularly back-end-of-line (BEOL) structures.

First claim

What is claimed is:

1 . A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
said memory array comprises 3-D structures;
said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
said non-memory circuit is not a part of any memory; and,
said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
a first die comprising the memory arrays of said plurality of SPU's; a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's; a plurality of inter-die connections communicatively coupling said first and second dice; wherein said off-die peripheral-circuit component comprises at least a portion of an address decoder of said memory array; and, said first and second dice have different back-end-of-line (BEOL) structures.

2 . The 3-D processor according to claim 1 , wherein said first and second dice are vertically stacked.

3 . The 3-D processor according to claim 2 , wherein said first and second dice have a same die size.

4 . The 3-D processor according to claim 2 , wherein all edges of said first and second dice are aligned.

5 . The 3-D processor according to claim 2 , wherein said each of said plurality of SPU's occupies a first area on said first die and a second area on said second die; and, said first and second areas coincide.

6 . The 3-D processor according to claim 1 , wherein a first total-number difference of BEOL layers between said memory array and said off-die peripheral-circuit component is larger than a second total-number difference of BEOL layers between said non-memory circuit and said off-die peripheral-circuit component.

7 . The 3-D processor according to claim 1 , wherein a third total-thickness difference of BEOL layers between said memory array and said off-die peripheral-circuit component is larger than a fourth total-thickness difference of BEOL layers between said non-memory circuit and said off-die peripheral-circuit component.

8 . The 3-D processor according to claim 1 , wherein said first die further comprises at least an in-die peripheral-circuit component of said memory array; and, a fifth total number of interconnect layers of said in-die peripheral-circuit component is smaller than a sixth total number of interconnect layers of said off-die peripheral-circuit component.

9 . The 3-D processor according to claim 1 , wherein said first die further comprises at least an in-die peripheral-circuit component of said memory array; and, at least a seventh portion of interconnect material in said in-die peripheral-circuit component has a higher resistivity than at least an eighth portion of interconnect material in said off-die peripheral-circuit component.

10 . The 3-D processor according to claim 1 , wherein said non-memory circuit is a logic circuit.

11 . The 3-D processor according to claim 1 , wherein said non-memory circuit is a processing circuit.

12 . The 3-D processor according to claim 1 , wherein said memory array is a random-access memory (RAM) array.

13 . The 3-D processor according to claim 1 , wherein said memory array is a non-volatile memory (NVM) array.

14 . The 3-D processor according to claim 1 , wherein said memory array is a three-dimensional memory (3D-M) array.

15 . A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof, wherein:
said memory array comprises 3-D structures;
said non-memory circuit and said off-die peripheral-circuit component are both 2-D circuits;
said non-memory circuit is not a part of any memory; and,
said non-memory circuit is communicatively coupled with said memory array through said off-die peripheral-circuit component;
a first die comprising the memory arrays of said plurality of SPU's; a second die comprising the non-memory circuits and the off-die peripheral-circuit components of the memory arrays of said plurality of SPU's; a plurality of inter-die connections communicatively coupling said first and second dice; wherein said off-die peripheral-circuit component comprises at least a portion of a sense amplifier of said memory array; and, said first and second dice have different back-end-of-line (BEOL) structures.

16 . The 3-D processor according to claim 15 , wherein said first and second dice are vertically stacked.

17 . The 3-D processor according to claim 16 , wherein said first and second dice have a same die size.

18 . The 3-D processor according to claim 16 , wherein all edges of said first and second dice are aligned.

19 . The 3-D processor according to claim 16 , wherein said each of said plurality of SPU's occupies a first area on said first die and a second area on said second die; and, said first and second areas coincide.

20 . The 3-D processor according to claim 15 , wherein a first total-number difference of BEOL layers between said memory array and said off-die peripheral-circuit component is larger than a second total-number difference of BEOL layers between said non-memory circuit and said off-die peripheral-circuit component.

21 . The 3-D processor according to claim 15 , wherein a third total-thickness difference of BEOL layers between said memory array and said off-die peripheral-circuit component is larger than a fourth total-thickness difference of BEOL layers between said non-memory circuit and said off-die peripheral-circuit component.

22 . The 3-D processor according to claim 15 , wherein said first die further comprises at least an in-die peripheral-circuit component of said memory array; and, a fifth total number of interconnect layers of said in-die peripheral-circuit component is smaller than a sixth total number of interconnect layers of said off-die peripheral-circuit component.

23 . The 3-D processor according to claim 15 , wherein said first die further comprises at least an in-die peripheral-circuit component of said memory array; and, at least a seventh portion of interconnect material in said in-die peripheral-circuit component has a higher resistivity than at least an eighth portion of interconnect material in said off-die peripheral-circuit component.

24 . The 3-D processor according to claim 15 , wherein said non-memory circuit is a logic circuit.

25 . The 3-D processor according to claim 15 , wherein said non-memory circuit is a processing circuit.

26 . The 3-D processor according to claim 15 , wherein said memory array is a random-access memory (RAM) array.

27 . The 3-D processor according to claim 15 , wherein said memory array is a non-volatile memory (NVM) array.

28 . The 3-D processor according to claim 15 , wherein said memory array is a three-dimensional memory (3D-M) array.

29 . A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a m

Assignees

• Zhang Guobiao
• Hong Kong Haicun Tech Co Limited

Inventors

• Zhang Guobiao

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• G06F18/21

  Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation · CPC title