Semiconductor package having reduced parasitic inductance

Patent metadata

Field	Value
Publication number	US-12575467-B2
Application number	US-202217946992-A
Country	US
Kind code	B2
Filing date	Sep 16, 2022
Priority date	Sep 16, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.

First claim

The invention claimed is:

1 . A semiconductor package comprising:
a lead frame comprising
one or more voltage input (Vin) leads;
a gate lead;
one or more switching node (Lx) leads;
a first die paddle;
a second die paddle; and
an end paddle;
a low side field-effect transistor (FET) being flipped and attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET and a drain electrode on a bottom surface of the low side FET; a high side FET attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET and a drain electrode on a bottom surface of the high side FET; a metal clip connecting the drain electrode of the low side FET and the source electrode of the high side FET to the end paddle of the lead frame; and a molding encapsulation enclosing the low side FET, the high side FET, the metal clip, and a majority portion of the lead frame; wherein each bottom surface of the one or more Vin leads, the gate lead, the one or more Lx leads, the first die paddle, the second die paddle, and the end paddle is exposed from the molding encapsulation; wherein a portion of the lead frame between the first die paddle and the second die paddle does not include a locking feature facilitating material integration of the lead frame and the molding encapsulation; and wherein a distance between a center of a first flat portion of the metal clip contacting the low side FET and a center of a second flat portion of the metal clip contacting the high side FET is less than two point four millimeters.

2 . The semiconductor package of claim 1 , wherein the semiconductor package is of a rectangular prism shape;
wherein a length of the semiconductor package is less than five millimeters; and wherein a width of the semiconductor package is less than six millimeters.

3 . The semiconductor package of claim 2 , wherein the length of the semiconductor package is three and half millimeters; and
wherein the width of the semiconductor package is five millimeters.

4 . The semiconductor package of claim 1 , wherein each of the exposed bottom surface of the one or more Lx leads is directly connected to the exposed bottom surface of the end paddle.

5 . The semiconductor package of claim 1 , wherein the semiconductor package is of a rectangular prism shape comprising
a first edge; and a second edge perpendicular to the first edge; wherein each of the exposed bottom surface of the one or more Lx leads is directly extended to the first edge; and wherein the exposed bottom surface of the gate lead is directly extended to the second edge.

6 . The semiconductor package of claim 5 , wherein a longitudinal direction of the exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads.

7 . The semiconductor package of claim 1 , wherein the distance is one point seven millimeters.

8 . The semiconductor package of claim 1 , wherein a first portion of the lead frame is of a full thickness;
wherein a second portion of the lead frame is of a partial thickness; and wherein an entirely of each of the one or more Vin leads is of the full thickness.

9 . The semiconductor package of claim 8 , wherein the partial thickness is half of the full thickness.

10 . The semiconductor package of claim 1 , wherein the semiconductor package is a DC-DC converter.

11 . A semiconductor package comprising:
a lead frame comprising
one or more voltage input (Vin) leads;
a gate lead;
one or more switching node (Lx) leads;
a first die paddle;
a second die paddle; and
an end paddle;
a low side field-effect transistor (FET) being flipped and attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET and a drain electrode on a bottom surface of the low side FET; a high side FET attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET and a drain electrode on a bottom surface of the high side FET; a metal clip connecting the drain electrode of the low side FET and the source electrode of the high side FET to the end paddle of the lead frame; and a molding encapsulation enclosing the low side FET, the high side FET, the metal clip, and a majority portion of the lead frame; wherein a distance between a center of a first flat portion of the metal clip contacting the low side FET and a center of a second flat portion of the metal clip contacting the high side FET is less than two point four millimeters.

12 . The semiconductor package of claim 11 , wherein a first portion of the lead frame is of a full thickness;
wherein a second portion of the lead frame is of a partial thickness; and wherein an entirely of each of the one or more Vin leads is of the full thickness.

13 . The semiconductor package of claim 12 , wherein the partial thickness is half of the full thickness.

14 . The semiconductor package of claim 11 , wherein the semiconductor package is a DC-DC converter.

15 . A semiconductor package comprising:
a lead frame comprising
one or more voltage input (Vin) leads;
a gate lead;
one or more switching node (Lx) leads;
a first die paddle;
a second die paddle; and
an end paddle;
a low side field-effect transistor (FET) being flipped and attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET and a drain electrode on a bottom surface of the low side FET; a high side FET attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET and a drain electrode on a bottom surface of the high side FET; a metal clip connecting the drain electrode of the low side FET and the source electrode of the high side FET to the end paddle of the lead frame; and a molding encapsulation enclosing the low side FET, the high side FET, the metal clip, and a majority portion of the lead frame; wherein the semiconductor package is of a rectangular prism shape comprising
a first edge; and
a second edge perpendicular to the first edge;
wherein each of the exposed bottom surface of the one or more Lx leads is directly extended to the first edge; wherein the exposed bottom surface of the gate lead is directly extended to the second edge; and wherein a distance between a center of a first flat portion of the metal clip contacting the low side FET and a center of a second flat portion of the metal clip contacting the high side FET is less than two point four millimeters.

16 . The semiconductor package of claim 15 , wherein a longitudinal direction of the exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads.

17 . The semiconductor package of claim 15 , wherein a first portion of the lead frame is of a full thickness;
wherein a second portion of the lead frame is of a partial thickness; and wherein an entirely of each of the one or more Vin leads is of the full thickness.

18 . The semiconductor package of claim 17 , wherein the partial thickness is half of the full thickness.

19 . The semiconductor package of claim 15 , wherein the semiconductor package is a DC-DC conve

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Xue Yan Xun
• Chen Lin
• Wang Long-Ching
• Ye Hui

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title