Method of making stacked multi-chip packaging structure

Patent metadata

Field	Value
Publication number	US-9230949-B2
Application number	US-201514641351-A
Country	US
Kind code	B2
Filing date	Mar 7, 2015
Priority date	Jul 31, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

First claim

What is claimed is:

1. A method for forming a stacked multi-chip packaging structure, the method comprising the steps of:
providing a lead frame comprising a first die paddle, a second die paddle and a plurality of pins separated from each other, wherein the second die paddle comprises a first part and a second part separated from each other;
attaching a first semiconductor chip to the first die paddle with an electrode at a back surface of the first semiconductor chip being electrically connected to the first die paddle;
flipping and attaching a second semiconductor chip to the second die paddle with an electrode at a front surface of the second semiconductor chip being electrically connected to the first part of the second die paddle and another electrode being electrically connected to the second part of the second die paddle;
attaching a metal clip to the first semiconductor chip and the second semiconductor chip with a bottom surface of metal clip being electrically connected to electrodes arranged on a front surface of the first semiconductor chip and an electrode arranged on a back surface of the flipped second semiconductor chip;
attaching a third semiconductor chip to a top surface of the metal clip with the third semiconductor chip being electrically isolated from the metal clip;
forming bonding wires between the electrodes of different semiconductor chips or between the electrode of a semiconductor chip and a pin; and
forming a plastic package body for encapsulating the third semiconductor chip, the metal clip, the first semiconductor chip and the second semiconductor chip and the lead frame which are stacked into a multi-layer structure in sequence, and then separating individual stacked multi-chip packaging structures by cutting through the plastic package body, wherein portions of the pin and portions of the back surface of the first die paddle and the second die paddle are exposed from the plastic package body for electrically connecting to an external device.

2. The method of claim 1 further comprising, before forming the plastic package body, attaching a heat sink to the top surface of the metal clip, wherein the heat sink thermally contacts the metal clip to improve heat dissipation through a top surface of the heat sink exposed from the plastic package body.

3. The method of claim 1 further comprising forming a notch on a top surface of the formed plastic package body; inserting a bottom part of a heat sink into the notch to thermally connect the heat sink with the top surface of the metal clip to improve heat dissipation through a top surface of the heat sink exposed from the top surface of the plastic package body.

4. The method of claim 1 , wherein the metal clip comprises a high-side connecting part attached to the first semiconductor chip and a low-side connecting part attached to the second semiconductor chip, and wherein the high-side connecting part and the low-side connecting part of the metal clip have the same or different thickness;
when a thickness of the high-side connecting part and the low-side connecting part is different, the third semiconductor chip is attached to a thinner part of the high-side connecting part or the low-side connecting part of the metal clip, and a thicker part of the high-side connecting part or the low-side connecting part is exposed from the plastic package body to improve heat dissipation.

5. The method of claim 1 , wherein a conductive adhesive is deposited between the first semiconductor chip and the first die paddle, between the second semiconductor chip and the second die paddle, and between the metal clip and the first semiconductor chip and the second semiconductor chip, and wherein a non-conductive adhesive is deposited between the third semiconductor chip and the metal clip.

6. The method of claim 1 , a sum of thicknesses of the metal clip and the first semiconductor chip and a sum of thicknesses of the metal clip and the second semiconductor chip are defined by a dimple formed in the metal clip, which further prevents the metal clip from tilting.

7. The method of claim 6 , wherein a first process for stacking the first semiconductor chip in the stacked multi-layer packaging structure comprises the steps of:
forming plating on a front surface of a silicon wafer comprising a plurality of first semiconductor chips;
performing semiconductor chip test;
grinding at a back surface of the silicon wafer to a predetermined thickness and depositing a metal layer on a back surface of the ground silicon wafer so as to form a back electrode;
cutting the silicon wafer to separate individual first semiconductor chips; and
attaching the back surface of the first semiconductor chip to the first die paddle.

8. The method of claim 7 , wherein a second process for stacking the second semiconductor chip in the stacked multi-layer packaging structure comprises the steps of:
forming plating on a front surface of another silicon wafer comprising a plurality of second semiconductor chips;
performing semiconductor chip test and mapping a circuitous pattern;
depositing a conductive ball on predetermined position of a front surface of the other silicon wafer to form a corresponding electrode;
forming a package body at chip scale package level to encapsulate the second semiconductor chip and the conductive ball;
grinding at the front surface of the second semiconductor chip to expose a top of the conductive ball from a top surface of the package body;
pre-cutting the front surface of the other silicon wafer to from a scribe line located between two adjacent second semiconductor chips;
grinding at a back surface of the other silicon wafer to a predetermined thickness and depositing a metal layer on a ground back surface of the other silicon wafer to form a corresponding back electrode;
cutting the other silicon wafer along the scribe line to separate individual second semiconductor chips; and
flipping and attaching the second semiconductor chip to the second die paddle.

9. The method of claim 8 , wherein a third process for stacking the third semiconductor chip in the stacked multi-layer packaging structure comprises the steps of:
grinding at a back surface of a wafer comprising a plurality of third semiconductor chips on a front surface of the wafer, wherein the wafer in ground to a predetermined thickness;
coating a non-conductive adhesive on a back surface of the third semiconductor chip;
cutting the wafer to separate individual third semiconductor chips;
attaching the third semiconductor chip to the top surface of the metal clip after the metal clip is attached to the first semiconductor chip and the second semiconductor chip;
attaching the stacked multi-layer structure including the third semiconductor chip, the metal clip, the first semiconductor chip and the second semiconductor chip to an adhesive tape for curing;
forming bonding wires between corresponding electrodes of different semiconductor chips and between the electrode of a semiconductor chip and the pin respectively;
forming the plastic package body for encapsulating the stacked multi-layer structure and the bonding wires, wherein the pin and the bottom surfaces of the first die paddle and the second die paddle are exposed from the plastic package body;
forming plating in exposed portions of the pin and the bottom surfaces of the first die paddle and the second die paddle; and
cutting the lead frame to separate individual package devices.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Zhang Xiaotian
• Pan Hua
• Lu Ming-Chen
• Lu Jun
• Yilmaz Hamza

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title