Semiconductor package having a lead frame including die paddles and method of making the same

Patent metadata

Field	Value
Publication number	US-11688671-B2
Application number	US-202117376054-A
Country	US
Kind code	B2
Filing date	Jul 14, 2021
Priority date	Jun 27, 2019
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor package, the method comprising the steps of:
providing a lead frame comprising
a first, second, third and fourth die paddles separated from one another, the first die paddle and the second die paddle facing each other, and the third die paddle and the fourth die paddle facing each other;

attaching a first low side field-effect transistor (FET), a second low side FET, a first high side FET, and a second high side FET to the first die paddle, the second die paddle, the third die paddle, and the fourth die paddle respectively;
connecting a drain electrode of the first low side FET to a source electrode of the first high side FET by a first metal clip;
connecting a drain electrode of the second low side FET to a source electrode of the second high side FET by a second metal clip;
forming a molding encapsulation enclosing the first low side FET, the second low side FET, the first high side FET, the second high side FET, the first metal clip, the second metal clip, and a majority portion of the lead frame; and
applying a singulation process separating the semiconductor package from adjacent semiconductor packages.

2. The method of claim 1 , wherein the first metal clip comprises an elevated section located at a center portion of the first metal clip; and
wherein the second metal clip comprises an elevated section located at a center portion of the second metal clip.

3. The method of claim 1 , before the step of forming the molding encapsulation, further comprising mounting a IC controller on the first metal clip and the second metal clip; and
applying a plurality of bonding wires connecting a plurality of electrodes of the IC controller to a plurality of pins of the lead frame respectively;
wherein a first end of the IC controller is mounted on the first metal clip through a first non-conductive adhesive;
wherein a second end of the IC controller is mounted on the second metal clip through a second non-conductive adhesive;
wherein the first end of the IC controller is above the first die paddle; and
wherein the second end of the IC controller is above the second die paddle.

4. The method of claim 3 , wherein the molding encapsulation further encloses the IC controller.

5. The method of claim 1 , before the step of forming the molding encapsulation, further comprising mounting an inductor on the first metal clip and the second metal clip;
wherein a first end of the inductor is mounted on the first metal clip through a first conductive adhesive;
wherein a second end of the inductor is mounted on the second metal clip through a second conductive adhesive;
wherein the first end of the inductor is above the third die paddle; and
wherein the second end of the inductor is above the fourth die paddle.

6. The method of claim 5 , before the step of forming the molding encapsulation, further comprising mounting an integrated circuit (IC) controller on the first metal clip and the second metal clip;
applying a plurality of bonding wires connecting a plurality of electrodes of the IC controller to a plurality of pins of the lead frame respectively;
wherein a first end of the IC controller is mounted on the first metal clip through a first non-conductive adhesive;
wherein a second end of the IC controller is mounted on the second metal clip through a second non-conductive adhesive;
wherein the first end of the IC controller is above the first die paddle; and
wherein the second end of the IC controller is above the second die paddle.

7. The method of claim 6 , wherein the molding encapsulation further encloses the inductor and the IC controller.

8. The method of claim 7 , wherein a bottom surface of the first die paddle is exposed from the molding encapsulation; a bottom surface of the second die paddle is exposed from the molding encapsulation; a bottom surface of the third die paddle is exposed from the molding encapsulation; and a bottom surface of the fourth die paddle is exposed from the molding encapsulation.

9. The method of claim 1 , wherein the first low side FET is flipped and attached to the first die paddle; and
wherein the second low side FET is flipped and attached to the second die paddle.

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Xue Yan Xun

Classifications

• H10W72/07653

  changes in shapes · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title