Back-end-of-line 2D memory cell

Patent metadata

Field	Value
Publication number	US-12575111-B2
Application number	US-202217855626-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 30, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques directed to creating back end of line 2D transistors that include a metal-ferroelectric-metal-insulator-semiconductor structure used as a memory cell. In embodiments, a combination wet etch and dry etch process may be used to form the 2D transistors. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A transistor structure comprising:
a first metal layer; a ferroelectric layer on the first metal layer; a second metal layer on the ferroelectric layer; an oxide layer on the second metal layer; a 2D layer on the oxide layer; a cap layer with a first side and a second side opposite the first side, wherein the first side of the cap layer is on a surface of the 2D layer; a dielectric layer, wherein a side of the dielectric layer is on the second side of the cap layer; a source that extends through the dielectric layer and through the cap layer to the surface of the 2D layer; a drain that extends through the dielectric layer and through the cap layer to the surface of the 2D layer; and wherein a portion of the source extends along a first portion of the side of the dielectric layer, wherein a portion of the drain extends along a second portion of the side of the dielectric layer, and wherein a portion of the cap layer is between the portion of the source and the portion of the drain.

2 . The transistor structure of claim 1 , wherein the source and the drain are substantially perpendicular to a plane of the surface of the 2D layer.

3 . The transistor structure of claim 1 , wherein the source and the drain are substantially parallel to each other.

4 . The transistor structure of claim 1 , wherein the source and the drain extend into the 2D layer.

5 . The transistor structure of claim 1 , wherein the cap layer includes a selected one or more of: Al, La, Hf, Ti, Zr, O, Al 2 O 3 , La 2 O 3 , HfO 2 , ZrO 2 , and/or TiO 2 .

6 . The transistor structure of claim 1 , wherein the dielectric layer includes a selected one or more of: silicon, oxygen, or nitrogen.

7 . The transistor structure of claim 1 , wherein the first metal layer or the second metal layer is a gate metal that includes a selected one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten.

8 . The transistor structure of claim 7 , wherein the oxide layer is a first oxide layer; and further comprising:
a second oxide layer that is substantially perpendicular to the surface of the 2D layer, wherein the second oxide layer at least partially surrounds the first metal layer, the ferroelectric layer, the second metal layer, the first oxide layer, the 2D layer, the cap layer, the dielectric layer, the source and the drain.

9 . The transistor structure of claim 1 , wherein the first metal layer is on an electrically conductive via.

10 . The transistor structure of claim 1 , wherein the transistor structure is a plurality of transistor structures, and wherein the plurality of transistor structures are physically coupled.

11 . The transistor structure of claim 1 , wherein the ferroelectric layer includes a selected one or more of: hafnium, oxygen, or zirconium.

12 . The transistor structure of claim 1 , wherein the transistor structure is a memory cell.

13 . A transistor structure comprising:
a first metal layer with a first oxide layer on the first metal layer; a 2D layer on the first oxide layer; a cap layer with a first side and a second side opposite the first side, wherein the first side of the cap layer is on a surface of the 2D layer; a dielectric layer, wherein a side of the dielectric layer is on the second side of the cap layer; a source and a drain that extends through the dielectric layer and through the cap layer to the surface of the 2D layer; a second oxide layer on the surface of the 2D layer, the second oxide layer between the source and the drain and physically coupled with the source and the drain; a second metal layer on the second oxide layer, wherein the second oxide layer electrically isolates the second metal layer from the 2D layer, the source, and the drain; a ferroelectric layer on the second metal layer; and a third metal layer on the ferroelectric layer, wherein the ferroelectric layer electrically isolates the second metal layer from the third metal layer.

14 . The transistor structure of claim 13 , wherein the source and the drain are substantially perpendicular to a plane of the surface of the 2D layer.

15 . The transistor structure of claim 13 , wherein the source and the drain are substantially parallel to each other.

16 . The transistor structure of claim 13 , wherein the cap layer includes a selected one or more of: Al, La, Hf, Ti, Zr, O, Al 2 O 3 , La 2 O 3 , HfO 2 , ZrO 2 , and/or TiO 2 .

17 . The transistor structure of claim 13 , wherein the dielectric layer includes a selected one or more of: silicon, oxygen, or nitrogen.

18 . The transistor structure of claim 13 , wherein the first metal layer, second metal layer, or third metal layer include a selected one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten.

19 . The transistor structure of claim 13 , wherein the dielectric layer is a first dielectric layer; and further comprising:
a second dielectric layer that is substantially perpendicular to the surface of the 2D layer, wherein the second dielectric layer at least partially surrounds the source, the drain, the first dielectric layer, the 2D layer, the first oxide layer, the second oxide layer, the first metal layer, the second metal layer, and the third metal layer.

20 . The transistor structure of claim 13 , wherein the ferroelectric layer includes a selected one or more of: hafnium, lanthanum, zirconium, and/or oxygen.

21 . The transistor structure of claim 13 , wherein the first metal layer is electrically coupled with an electrically conductive via.

22 . The transistor structure of claim 13 , wherein the transistor structure forms a memory cell.

Assignees

• Intel Corp

Inventors

• Lin Chia-Ching
• Shivaraman Shriram
• O'Brien Kevin P
• Penumatcha Ashish Verma
• Dorow Chelsey
• Maxey Kirby
• Naylor Carl H
• Lee Sudarat
• Avci Uygar E
• Chang Sou-Chi

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title