Merged cavities and buried etch stops for three-dimensional memory arrays

Patent metadata

Field	Value
Publication number	US-12575102-B2
Application number	US-202217884299-A
Country	US
Kind code	B2
Filing date	Aug 9, 2022
Priority date	Jun 2, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Methods, systems, and devices for merged cavities and buried etch stops for three-dimensional memory arrays are described. For example, a row of cavities may be formed using a cavity etching process and material separating cavities of the row may be removed to merge the row of cavities to form a trench. In some cases, a trench may be formed from multiple rows of cavities. Additionally, or alternatively, a trench may be formed from a pattern of cavities that includes different quantities of rows at different locations along the trench. In some examples, etch stopping material portions (e.g., etch stops) may be formed at locations corresponding to cavities prior to the cavity etching process. For example, exposed material surfaces at locations corresponding to cavities or trenches may be oxidized to form etch stops.

First claim

What is claimed is:

1 . A method, comprising:
depositing a first stack of material layers over a substrate; forming a plurality of first trenches through at least a portion of each material layer of the first stack of material layers; forming a plurality of first cavities through at least a portion of each material layer of the first stack of material layers; forming a first plurality of first material portions based at least in part on depositing one or more first materials in the plurality of first trenches; forming a second plurality of first material portions based at least in part on depositing the one or more first materials in the plurality of first cavities; depositing a second stack of material layers over the first stack of material layers, the second stack of material layers comprising alternating layers of a second material and a third material; forming a plurality of second cavities through the second stack of material layers, wherein forming each second cavity of the plurality of second cavities exposes a portion of a first material portion of the first plurality of first material portions; forming a plurality of third cavities through the second stack of material layers, wherein forming each third cavity of the plurality of third cavities exposes a portion of a first material portion of the second plurality of first material portions; forming a plurality of second trenches based at least in part on removing portions of the second stack of material layers to merge second cavities of the plurality of second cavities; and forming a plurality of memory cells based at least in part on depositing a semiconductor material in the plurality of third cavities.

2 . The method of claim 1 , wherein depositing the one or more first materials in the plurality of first trenches and depositing the one or more first materials in the plurality of first cavities are performed concurrently.

3 . The method of claim 1 , wherein forming the plurality of second cavities and forming the plurality of third cavities are performed concurrently.

4 . The method of claim 1 , wherein each second trench of the plurality of second trenches is associated with multiple rows of second cavities along the second trench.

5 . The method of claim 1 , wherein each second trench of the plurality of second trenches is associated with a first quantity of rows of second cavities along a first portion of the second trench and a second quantity of rows of second cavities along a second portion of the second trench.

6 . The method of claim 1 , wherein each second cavity of the plurality of second cavities is formed with an elliptical opening having a minor axis aligned along a direction of an associated second trench of the plurality of second trenches.

7 . The method of claim 1 , further comprising:
forming a plurality of first voids based at least in part on removing the third material from the second stack of material layers; and forming a plurality of word lines coupled with the plurality of memory cells based at least in part on depositing one or more first conductive materials in the plurality of first voids.

8 . The method of claim 1 , further comprising:
forming a plurality of second voids based at least in part on removing the second plurality of first material portions; and forming a plurality of transistors based at least in part on depositing a semiconductor and a gate dielectric in the plurality of second voids.

9 . The method of claim 1 , wherein forming the first plurality of first material portions and the second plurality of first material portions comprises:
depositing one or more metallic materials in the plurality of first trenches and in the plurality of first cavities.

10 . The method of claim 1 , further comprising:
depositing a layer of a conductive material over the substrate, wherein the first stack of material layers is deposited over the layer of the conductive material.

11 . An apparatus formed by a process comprising:
depositing a first stack of material layers over a substrate; forming a plurality of first trenches through at least a portion of each material layer of the first stack of material layers; forming a plurality of first cavities through at least a portion of each material layer of the first stack of material layers; forming a first plurality of first material portions based at least in part on depositing one or more first materials in the plurality of first trenches; forming a second plurality of first material portions based at least in part on depositing the one or more first materials in the plurality of first cavities; depositing a second stack of material layers over the first stack of material layers, the second stack of material layers comprising alternating layers of a second material and a third material; forming a plurality of second cavities through the second stack of material layers, wherein forming each second cavity of the plurality of second cavities exposes a portion of a first material portion of the first plurality of first material portions; forming a plurality of third cavities through the second stack of material layers, wherein forming each third cavity of the plurality of third cavities exposes a portion of a first material portion of the second plurality of first material portions; forming a plurality of second trenches based at least in part on removing portions of the second stack of material layers to merge second cavities of the plurality of second cavities; and forming a plurality of memory cells based at least in part on depositing a semiconductor material in the plurality of third cavities.

12 . The apparatus of claim 11 , formed by the process comprising:
forming the plurality of second cavities concurrently with forming the plurality of third cavities.

13 . The apparatus of claim 11 , wherein each second trench of the plurality of second trenches is associated with multiple rows of second cavities along the second trench.

14 . The apparatus of claim 11 , wherein each second trench of the plurality of second trenches is associated with a first quantity of rows of second cavities along a first portion of the second trench and a second quantity of rows of second cavities along a second portion of the second trench.

15 . The apparatus of claim 11 , wherein each second cavity of the plurality of second cavities is formed with an elliptical opening having a minor axis aligned along a direction of an associated second trench of the plurality of second trenches.

16 . The apparatus of claim 11 , formed by the process further comprising:
forming a plurality of first voids based at least in part on removing the third material from the second stack of material layers; and forming a plurality of word lines coupled with the plurality of memory cells based at least in part on depositing one or more first conductive materials in the plurality of first voids.

17 . The apparatus of claim 11 , formed by the process further comprising:
forming a plurality of second voids based at least in part on removing the second plurality of first material portions; and forming a plurality of transistors based at least in part on depositing a semiconductor and a gate dielectric in the plurality of second voids.

18 . An apparatus, comprising:
a first array region comprising a first plurality of memory cells and a first plurality of access lines coupled with the first plurality of memory cells, the first plurality of access lines arranged between first layers of a first diele

Assignees

• Micron Technology Inc

Inventors

• Fukuzumi Yoshiaki
• Wells David H
• Kim Byeung Chul
• Hill Richard J
• Tessariol Paolo

Classifications

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title