Three-dimensional integration schemes for reducing fluorine-induced electrical shorts

Patent metadata

Field	Value
Publication number	US-9799671-B2
Application number	US-201514680414-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Apr 7, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or using of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide can be employed as an insulating spacer on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a backside blocking dielectric layer;
an array of memory openings extending through the stack; and
a plurality of memory stack structures located within a respective memory opening, wherein:
the electrically conductive layers comprise composite electrically conductive layers; and
each composite electrically conductive layer comprises:
a doped semiconductor material portion directly physically contacting a horizontal bottom surface of a respective overlying portion of the backside blocking dielectric layer, a horizontal top surface of a respective underlying portion of the backside blocking dielectric layer, and a sidewall surface of a respective vertical portion of the backside blocking dielectric layer;
a metallic material portion electrically shorted to the doped semiconductor material portion and laterally spaced from a most proximal memory stack structure by at least the doped semiconductor material portion and directly physically contacting a horizontal bottom surface of a respective overlying portion of the backside blocking dielectric layer and a horizontal top surface of a respective underlying portion of the backside blocking dielectric layer; and
a metal-semiconductor alloy portion directly physically contacting the doped semiconductor material portion, the metallic material portion, a horizontal bottom surface of a respective overlying portion of the backside blocking dielectric layer, and a horizontal top surface of a respective underlying portion of the backside blocking dielectric layer.

2. The monolithic three-dimensional memory device of claim 1 , wherein the backside blocking dielectric layer comprises a dielectric metal oxide.

3. The monolithic three-dimensional memory device of claim 1 , wherein a contiguous space extending between a neighboring pair of memory stack structures within a level of one of the electrically conductive layers excludes the metallic material portion.

4. The monolithic three-dimensional memory device of claim 1 , wherein each metallic material portion comprises:
a metallic liner portion comprising a conductive metallic compound of at least one elemental metal and a non-metallic element and contacting a respective doped semiconductor material portion; and
a metal fill portion comprising at least one elemental metal and laterally spaced from the respective doped semiconductor material portion by the metallic liner portion.

5. The monolithic three-dimensional memory device of claim 1 , wherein each of the plurality of memory stack structures comprises a vertical stack of memory elements, a tunneling dielectric layer, and a vertical semiconductor channel.

6. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

the composite electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

7. The monolithic three-dimensional memory device of claim 1 , wherein the metal-semiconductor alloy portion comprises an alloy of a semiconductor material of the doped semiconductor material portion and an elemental metal or an intermetallic alloy of at least two elemental metals of the metallic material portion.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pachamuthu Jayavel
• Baenninger Matthias
• Shi Stephen
• Alsmeier Johann

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01L21/768

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic