Semiconductor device having concave lower sidewall portion on gate structure

Patent metadata

Field	Value
Publication number	US-12575079-B2
Application number	US-202217750723-A
Country	US
Kind code	B2
Filing date	May 23, 2022
Priority date	Oct 12, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a gate structure on a substrate, a sidewall of the gate structure including,
a concave lower sidewall portion, and
an upper sidewall portion that is vertical with respect to an upper surface of the substrate,
a first gate spacer on the upper sidewall portion of the sidewall of the gate structure; and a second gate spacer on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer, wherein the second gate spacer contacts a lower surface of the first gate spacer and includes nitride, wherein the gate structure includes a first dielectric pattern adjacent to the upper surface of the substrate, and wherein the lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern.

2 . The semiconductor device according to claim 1 , wherein a cross-section of the second gate spacer in a vertical direction with respect to the upper surface of the substrate has an “L” shape.

3 . The semiconductor device according to claim 1 ,
wherein the first dielectric pattern includes silicon oxide, and wherein a sidewall of the first dielectric pattern includes a portion defining the concave lower sidewall portion of the gate structure.

4 . The semiconductor device according to claim 3 ,
wherein the gate structure further includes a second dielectric pattern, a first conductive pattern, a barrier pattern, and a second conductive pattern sequentially stacked on the first dielectric pattern in a vertical direction with respect to the upper surface of the substrate, and wherein the second dielectric pattern includes a material having a dielectric constant higher than a dielectric constant of silicon oxide.

5 . The semiconductor device according to claim 1 , further comprising:
a third gate spacer on an outer sidewall of the second gate spacer, wherein the third gate spacer includes silicon oxide.

6 . The semiconductor device according to claim 5 , wherein a volume of the third gate spacer is greater than a sum of volumes of the first gate spacer and the second gate spacer.

7 . The semiconductor device according to claim 1 , wherein an entire portion of the lower surface of the first gate spacer contacts the second gate spacer.

8 . The semiconductor device according to claim 1 , further comprising impurity regions at upper portions of the substrate that are adjacent to the gate structure.

9 . A semiconductor device comprising:
a gate structure on a substrate, the gate structure including a first dielectric pattern containing silicon oxide; a first gate spacer contacting an upper portion of a sidewall of the gate structure, the first gate spacer including silicon nitride; and a second gate spacer contacting a lower portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer, the second gate spacer including silicon nitride, wherein a lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern, and the second gate spacer does not contact an upper portion of a sidewall of the first dielectric pattern but contacts a lower portion of the sidewall of the first dielectric pattern.

10 . The semiconductor device according to claim 9 , wherein the lower portion of the sidewall of the first dielectric pattern contacts the second gate spacer is concave.

11 . The semiconductor device according to claim 10 , wherein the second gate spacer contacts the lower surface of the first gate spacer.

12 . The semiconductor device according to claim 9 , wherein a cross-section of the second gate spacer in a vertical direction with respect to an upper surface of the substrate has an “L” shape.

13 . The semiconductor device according to claim 9 , further comprising:
a third gate spacer contacting an outer sidewall of the second gate spacer, wherein the third gate spacer includes silicon oxide.

14 . The semiconductor device according to claim 13 , wherein a volume of the third gate spacer is greater than a sum of volumes of the first gate spacer and the second gate spacer.

15 . The semiconductor device according to claim 9 , further comprising impurity regions at upper portions of the substrate adjacent to the gate structure.

16 . The semiconductor device according to claim 9 ,
wherein the gate structure further includes a second dielectric pattern, a first conductive pattern, a barrier pattern, and a second conductive pattern sequentially stacked on the first dielectric pattern in a vertical direction with respect to the upper surface of the substrate, wherein the second dielectric pattern includes a material having a dielectric constant higher than a dielectric constant of silicon oxide, and wherein a sidewall of the second dielectric pattern contacts the first gate spacer.

17 . A semiconductor device comprising:
a substrate including a cell region and a peripheral circuit region surrounding the cell region; a first active pattern on the cell region of the substrate; a second active pattern on the peripheral circuit region of the substrate; an isolation pattern covering sidewalls of the first active pattern and the second active pattern; a first gate structure buried at upper portions of the first active pattern and the isolation pattern, the first gate structure extending in a first direction substantially parallel to an upper surface of the substrate; a second gate structure on the second active pattern, a sidewall of the second gate structure including,
a concave lower sidewall portion, and
an upper sidewall portion that is vertical with respect to the upper surface of the substrate,
a gate spacer structure including,
a first gate spacer on the upper sidewall portion of the sidewall of the second gate structure,
a second gate spacer on the concave lower sidewall portion of the sidewall of the second gate structure and an outer sidewall of the first gate spacer, the second gate spacer contacting a lower surface of the first gate spacer and including silicon nitride, and
a third gate spacer on an outer sidewall of the second gate spacer;
a bit line structure contacting a central upper surface of the first active pattern, the bit line structure extending in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; a contact plug structure contacting each of opposite edge upper surfaces of the first active pattern; and a capacitor on the contact plug structure, wherein the second gate structure includes a first dielectric pattern adjacent to the upper surface of the substrate, and wherein the lower surface of the first gate spacer is lower than an upper surface of the first dielectric pattern.

18 . The semiconductor device according to claim 17 ,
wherein the second gate structure includes a second dielectric pattern, a first conductive pattern, a barrier pattern, and a second conductive pattern sequentially stacked on the second active pattern in a vertical direction with respect to the upper surface of the substrate, and wherein the first dielectric pattern includes silicon oxide, and the second dielectric pattern includes a material having a dielectric constant higher than a dielectric constant of silicon oxide.

19 . The semiconductor device according to claim 17 , further comprising impurity regions at upper portions of the substrate adjacent to the second gate structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hyebin
• Yoon Chansic
• Kil Gyuhyun
• Back Doosan
• Cho Hyungki
• HAN Junghoon

Classifications

• H10D64/021 Primary

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/01334

  by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title