Semiconductor device

Patent metadata

Field	Value
Publication number	US-11545554-B2
Application number	US-202117406162-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Dec 14, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer, the gate insulating layer including a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer;
a first spacer on a side surface of the gate stack; and
a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

2. The semiconductor device of claim 1 , wherein the protruding portion at least partially overlaps the first spacer.

3. The semiconductor device of claim 1 , wherein the first spacer is disposed on an upper surface of the first dielectric layer.

4. The semiconductor device of claim 1 , wherein the first dielectric layer has a side surface defining a concave portion recessed towards a center of the first dielectric layer, and
the protruding portion fills at least a portion of the concave portion.

5. The semiconductor device of claim 1 , further comprising:
a third spacer between the first spacer and the second spacer and having a dielectric constant less than the dielectric constant of the first spacer.

6. The semiconductor device of claim 1 , wherein a lower surface of the second spacer is disposed at a level higher than a lower surface of the first dielectric layer.

7. The semiconductor device of claim 1 , wherein the dielectric constant of the first spacer is greater than the dielectric constant of the first dielectric layer and less than the dielectric constant of the second dielectric layer.

8. The semiconductor device of claim 1 , wherein the first spacer is disposed between the second dielectric layer and the second spacer.

9. The semiconductor device of claim 1 , wherein an oxygen content ratio of the second spacer is greater than an oxygen content ratio of the first spacer.

10. The semiconductor device of claim 1 , wherein the second spacer comprises SIOCN.

11. A semiconductor device, comprising:
a gate stack on a substrate, the gate stack including a gate insulating layer and a gate electrode on the gate insulating layer, the gate insulating layer including a first dielectric layer and a second dielectric layer on the first dielectric layer, wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer;
a spacer structure on a side surface of the gate stack, the spacer structure including a first spacer and a second spacer on the first spacer, wherein a dielectric constant of the second spacer is less than a dielectric constant of the first spacer;
an interlayer insulating layer covering the spacer structure; and
a contact plug penetrating the interlayer insulating layer to connect the substrate,
wherein the contact plug includes a first side surface adjacent to the second spacer and a second side surface opposite to the first side surface, and
the first side surface has a sunken region recessed towards the second side surface.

12. The semiconductor device of claim 11 , wherein an uppermost portion of the sunken region is disposed at a level lower than an upper surface of the first spacer.

13. The semiconductor device of claim 11 , wherein a side surface of the second spacer has a rounded shape, and
the first side surface of the contact plug extends along the side surface of the second spacer.

14. The semiconductor device of claim 11 , wherein the contact plug directly contacts a side surface of the second spacer.

15. The semiconductor device of claim 11 , wherein the first spacer is disposed on an upper surface of the first dielectric layer.

16. The semiconductor device of claim 11 , wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer.

17. The semiconductor device of claim 11 , further comprising:
a third spacer between the first spacer and the second spacer, wherein a dielectric constant of the third spacer less than the dielectric constant of the first spacer.

18. A semiconductor device, comprising:
a first dielectric layer on a substrate, the first dielectric layer having a side surface defining a concave portion recessed towards a center of the first dielectric layer;
a second dielectric layer on the first dielectric layer, wherein a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer;
a gate electrode on the second dielectric layer;
a gate capping pattern on the gate electrode;
a first spacer on a side surface of the second dielectric layer and a side surface of the gate electrode;
a second spacer on the first spacer;
a third spacer between the first spacer and the second spacer and filling at least a portion of the concave portion;
an interlayer insulating layer covering the third spacer and the gate capping pattern; and
a contact plug penetrating the interlayer insulating layer to connect the substrate,
wherein a dielectric constant of the second spacer is less than the dielectric constant of the first spacer and greater than a dielectric constant of the third spacer.

19. The semiconductor device of claim 18 , wherein the second spacer includes a protruding portion extending from a level of a lower surface of the first spacer towards the first dielectric layer.

20. The semiconductor device of claim 18 , wherein a lower surface of the second spacer is higher than a lower surface of the first dielectric layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Back Doosan
• Kim Dongoh
• Kil Gyuhyun
• Han Jung-Hoon

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L29/513

  Electricity · mapped topic

• H01L29/41725

  Electricity · mapped topic

• H01L29/42368 Primary

  Electricity · mapped topic

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title