Method and device having low contact resistance

Patent metadata

Field	Value
Publication number	US-10446684-B2
Application number	US-201815935888-A
Country	US
Kind code	B2
Filing date	Mar 26, 2018
Priority date	May 19, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate and a gate structure on the semiconductor substrate. The gate structure includes a gate dielectric layer on the semiconductor substrate, a gate on the gate dielectric layer, and a spacer layer on opposite sides of the gate. The method also includes etching the semiconductor substrate to form first and second recesses, etching a portion of the spacer layer to expose a surface portion of the semiconductor substrate, and forming a source filling the first recess and a drain filling the second recess. The source (drain) includes a first source (drain) portion in the first (second) recess and a second source (drain) portion on the first source (drain) portion. The second source portion or the second drain portion covers the exposed surface portion of the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a gate structure on the semiconductor substrate and comprising a gate dielectric layer, a gate on the gate dielectric layer, a spacer layer on opposite sides and an upper surface of the gate;
a first recess and a second recess in the semiconductor substrate and on opposite sides of the gate structure;
a source filling the first recess and including a first source portion in the first recess and a second source portion on the first source portion, and a drain filing the second recess and including a first drain portion in the second recess and a second drain portion on the first drain portion;
wherein the second source portion covers a first surface portion of the semiconductor substrate between the spacer layer and the first recess, or the second drain portion covers a second surface portion of the semiconductor substrate between the spacer layer and the second recess.

2. The semiconductor device of claim 1 , further comprising a notch at a lower portion of the spacer layer, wherein the notch is filled with the second source portion or the second drain portion.

3. The semiconductor device of claim 1 , wherein:
the second source portion has a doping concentration greater than a doping concentration of the first source portion;
the second drain portion has a doping concentration greater than a doping concentration of the first drain portion.

4. The semiconductor device of claim 1 , wherein:
the first source portion and the first drain portion each comprise silicon germanium, silicon carbide, or silicon phosphide;
the second source portion and the second drain portion each comprise silicon.

5. The semiconductor device of claim 1 , further comprising a seed layer in the first recess and the second recess, wherein the first source portion and the first drain portion are on the seed layer.

6. The semiconductor device of claim 5 , wherein the seed layer, the first source portion, and the first drain portion each comprise silicon germanium, and the first source portion and the first drain portion each comprise a germanium concentration that is greater than a germanium concentration of the seed layer.

7. The semiconductor device of claim 5 , wherein the first source portion and the first drain portion each comprise carbon, fluorine, and/or nitrogen.

8. The semiconductor device of claim 1 , wherein the source and the drain each comprise carbon, fluorine, and/or nitrogen.

9. The semiconductor device of claim 1 , wherein the spacer layer comprises:
a first spacer layer on sidewalls and on the upper surface of the gate;
a second spacer layer on sidewalls of the first spacer layer; and
a third spacer layer on sidewalls of the second spacer layer.

10. The semiconductor device of claim 1 , wherein:
the first spacer layer comprises silicon nitride;
the second spacer layer comprises silicon dioxide; and
the third spacer layer comprises silicon nitride.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhao Meng

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P14/274

  using seed materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title