Quantization error and spur mitigation in a digital phase-locked loop

Patent metadata

Field	Value
Publication number	US-12574036-B2
Application number	US-202418808447-A
Country	US
Kind code	B2
Filing date	Aug 19, 2024
Priority date	Aug 19, 2024
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A digital phase-locked loop (DPLL) may include a dithering source to provide a dithering signal that is on an order of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal, a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dithering signal in association with cancelling an effect of the dithering signal on the DPLL output signal, and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association with cancelling an effect of a quantization error of the primary DSM.

First claim

What is claimed is:

1 . A digital phase-locked loop (DPLL), comprising:
a dithering source to provide a dithering signal, wherein the dithering signal is on an order of up to one integer bit on a set of fractional bits of a modulation signal; a digitally controlled oscillator (DCO) to generate a DPLL output signal based at least in part on the modulation signal, wherein the DCO comprises a primary capacitor bank, a first auxiliary capacitor bank, and a second auxiliary capacitor bank; a primary delta-sigma modulator (DSM) to drive the primary capacitor bank based on the dithering signal and the modulation signal; a first auxiliary DSM to drive the first auxiliary capacitor bank based on the dithering signal in association with cancelling an effect of the dithering signal on the DPLL output signal; and a second auxiliary DSM to drive the second auxiliary capacitor bank based on the modulation signal and the dithering signal in association with cancelling an effect of a quantization error of the primary DSM on the DPLL output signal.

2 . The DPLL of claim 1 , wherein the second auxiliary DSM is to drive the second auxiliary capacitor bank in association with cancelling an effect of a quantization error of the first auxiliary DSM on the DPLL output signal.

3 . The DPLL of claim 1 , wherein the dithering signal is to scramble generation of the quantization error of the primary DSM so as to remove periodicity from the quantization error of the primary DSM.

4 . The DPLL of claim 1 , wherein the dithering signal is a zero mean signal.

5 . The DPLL of claim 1 , wherein an input signal of the primary DSM is a signal that results from summing the dithering signal and the modulation signal.

6 . The DPLL of claim 1 , wherein an input signal of the first auxiliary DSM is a signal that results from inverting and scaling the dithering signal.

7 . The DPLL of claim 1 , wherein an input signal of the second auxiliary DSM is a signal that results from summing a scaled difference signal associated with the primary DSM and a scaled difference signal associated with the first auxiliary DSM.

8 . The DPLL of claim 1 , wherein the first auxiliary capacitor bank has a first gain factor and the second auxiliary capacitor bank has a second gain factor.

9 . The DPLL of claim 1 , wherein a first gain is applied on a signal path of the first auxiliary DSM and a second gain is applied on a signal path of the second auxiliary DSM.

10 . A digital phase-locked loop (DPLL), comprising:
a dithering source to provide a dithering signal that causes periodicity to be eliminated from a quantization error of a primary delta-sigma modulator (DSM) of the DPLL; a primary signal path comprising the primary DSM; a first auxiliary signal path comprising a first auxiliary DSM associated with cancelling an effect of the dithering signal on an output signal of the DPLL; and a second auxiliary signal path comprising a second auxiliary DSM associated with cancelling an effect of the quantization error of the primary DSM on the output signal of the DPLL.

11 . The DPLL of claim 10 , wherein the second auxiliary DSM is associated with cancelling an effect of a quantization error of the first auxiliary DSM on the output signal of the DPLL.

12 . The DPLL of claim 10 , wherein the dithering signal is on an order of up to one integer bit on a set of fractional bits of a modulation signal.

13 . The DPLL of claim 10 , wherein the dithering signal is to scramble generation of the quantization error of the primary DSM.

14 . The DPLL of claim 10 , wherein the dithering signal is a zero mean signal.

15 . The DPLL of claim 10 , wherein an input signal of the primary DSM is a signal that results from summing the dithering signal and a modulation signal.

16 . The DPLL of claim 10 , wherein an input signal of the first auxiliary DSM is a signal that results from inverting and scaling the dithering signal.

17 . The DPLL of claim 10 , wherein an input signal of the second auxiliary DSM is a signal that results from summing a scaled difference signal associated with the primary DSM and a scaled difference signal associated with the first auxiliary DSM.

18 . The DPLL of claim 10 , wherein a first gain is applied on a signal path of the first auxiliary DSM and a second gain is applied on a signal path of the second auxiliary DSM, the second gain being different from the first gain.

19 . The DPLL of claim 10 , further comprising a digitally controlled oscillator (DCO) comprising a primary capacitor bank on the primary signal path, a first auxiliary capacitor bank on the first auxiliary signal path, and a second auxiliary capacitor bank on the second auxiliary signal path.

20 . A digital phase-locked loop (DPLL), comprising:
a dithering source to provide a dithering signal, wherein the dithering signal is on an order of up to one integer bit on a set of fractional bits of a modulation signal; a digitally controlled oscillator (DCO) to generate a DPLL output signal based at least in part on the modulation signal; a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dithering signal and the modulation signal; and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dithering signal in association cancelling an effect of at least a quantization error of the primary DSM on the DPLL output signal.

21 . The DPLL of claim 20 , further comprising a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dithering signal in association cancelling an effect of the dithering signal on the DPLL output signal.

22 . The DPLL of claim 21 , wherein the second auxiliary DSM is to drive the second auxiliary capacitor bank in association with cancelling an effect of a quantization error of the first auxiliary DSM on the DPLL output signal.

Assignees

• Infineon Technologies Ag

Inventors

• Grimaldi Luigi
• Cherniak Dmytro
• Versolatto Fabio
• Boi Giovanni
• Padovan Fabio

Classifications

• H03M3/328 Primary

  using dither · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title