Digital Phase Locked Loops

Patent metadata

Field	Value
Publication number	US-2017194973-A1
Application number	US-201615377917-A
Country	US
Kind code	A1
Filing date	Dec 13, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.

First claim

1 . An all digital phase locked loop system for providing a variable frequency output signal which tracks a variable frequency input signal, comprising:
a digital phase locked loop, including a digitally controlled oscillator having an output arranged to provide a variable frequency output signal; and a model of the digitally controller oscillator, wherein the model represents the behaviour of the digitally controlled oscillator as a function of frequency, the model having a model input arranged to receive a signal indicating a current target frequency of a variable frequency input signal, wherein the model of the digitally controlled oscillator is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency and wherein the digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator for the current target frequency.

2 . The all digital phase locked loop system as claimed in claim 1 , wherein the digital phase locked loop includes a filter and wherein the at least one control signal is arranged to modify an output signal of the filter to control the frequency of the digitally controlled oscillator.

3 . The all digital phase locked loop system as claimed in claim 1 , wherein the at least one control signal is supplied to the digitally controlled oscillator to control the frequency of the digitally controlled oscillator.

4 . The all digital phase locked loop system as claimed in claim 1 , wherein the model is configured to output a plurality of control signals comprising a first control signal providing coarse control, a second control signal providing moderate control and a third control signal providing fine control.

5 . The all digital phase locked loop system as claimed in claim 4 , wherein the phase locked loop includes a filter and the first, second and third control signals are arranged to modify respective first, second and third output signals of the filter to control the frequency of the digitally controlled oscillator.

6 . The all digital phase locked loop system as claimed in claim 4 , wherein the phase locked loop includes a filter and the first and second control signals are supplied to the digitally controlled oscillator to control its frequency and the third control signal is arranged to modify an output signal of the filter to control the frequency of the digitally controlled oscillator.

7 . The all digital phase locked loop system as claimed in claim 1 , wherein the digitally controlled oscillator includes a plurality of variable capacitance elements and wherein the or each control signal is used to change the capacitance of the variable capacitance elements to change the frequency of the digitally controlled oscillator.

8 . The all digital phase locked loop system as claimed in claim 7 , wherein the plurality of variable capacitance elements are capacitor banks and the model is configured to implement a model of a digitally controlled oscillator including a plurality of capacitor banks each having a different frequency resolution.

9 . The all digital phase locked loop system as claimed in claim 1 , wherein the model includes at least one look up table.

10 . The all digital phase locked loop system as claimed in claim 1 , wherein the model is further configured to interpolate between a first value and a second value of the current target frequency.

11 . The all digital phase locked loop system as claimed in claim 1 , wherein the phase locked loop includes a filter and wherein the filter is configured to output a pre-set value when a transition between a rising and a falling, or a falling and a rising, frequency ramp signal is detected.

12 . The all digital phase locked loop system as claimed in claim 1 , wherein the phase locked loop includes a filter and wherein the model is configured to update values stored in the model based on one or more signals output from the filter.

13 . A package comprising a lead frame and a semi-conductor integrated circuit, wherein the semi-conductor integrated circuit is configured to provide the all digital phase locked loop system of claim 1 .

14 . A continuous wave radar system including:
a variable frequency oscillator arranged to drive a transmission antenna; and a modulation circuit arranged to supply a frequency modulation signal to modulate the frequency of the variable frequency oscillator, wherein the modulation circuit includes an all digital phase locked loop system as claimed in claim 1 .

15 . A method for providing a variable frequency output signal which tracks a variable frequency input signal, comprising:
supplying a signal indicating a current target frequency for the variable frequency input signal to a model of a digitally controlled oscillator; generating at least one control signal using the model of the digitally controlled oscillator; using the control signal to control the frequency of a digitally controlled oscillator forming part of a phase locked loop to be closer to the current target frequency; and
using the phase locked loop to further control the frequency of the digitally controlled oscillator to reduce any differences between the frequency of the digitally controlled oscillator and the target frequency arising from any deviations of the model of the digitally controlled oscillator form the digitally controlled oscillator for the current target frequency.

Assignees

• Nxp Bv

Inventors

• Moehlmann Ulrich

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• G01S7/35

  Details of non-pulse systems · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title