Semiconductor devices and methods of operating the same

Patent metadata

Field	Value
Publication number	US-10516405-B2
Application number	US-201816027646-A
Country	US
Kind code	B2
Filing date	Jul 5, 2018
Priority date	Jan 8, 2018
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A semiconductor device includes a time-to-digital converter (TDC) that receives a reference frequency signal and a feedback frequency signal, and outputs a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal; a digital loop filter (DLF) that outputs a second digital signal generated by filtering the first digital signal; a multiplier circuit that outputs one of a third digital signal and a final test signal, the third digital signal generated by performing a multiplication operation on the second digital signal using a multiplication coefficient; a digital-controlled oscillator (DCO) that generates an oscillation signal having a frequency based on the output one of the third digital signal and the final test signal; and a loop gain calibrator (LGC) that receives the oscillation signal, generates a pair of test signals, and determines the multiplication coefficient using the pair of test signals.

First claim

What is claimed is:

1. A semiconductor device comprising:
a time-to-digital converter (TDC) configured to
receive a reference frequency signal and a feedback frequency signal, and
output a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal;

a digital loop filter (DLF) configured to output a second digital signal generated by filtering the first digital signal;
a multiplier circuit configured to output one of a third digital signal and a final test signal, the third digital signal being generated by performing a multiplication operation on the second digital signal using a multiplication coefficient;
a digital-controlled oscillator (DCO) configured to generate an oscillation signal having an oscillation signal frequency based on the output one of the third digital signal and the final test signal; and
a loop gain calibrator (LGC) configured to
receive the oscillation signal,
generate a pair of test signals, and
determine the multiplication coefficient using the pair of test signals.

2. The semiconductor device of claim 1 , wherein
the pair of test, signals include first and second test signals,
a frequency of the first test signal is lower than the oscillation signal frequency by as much as a first frequency, and
a frequency of the second test signal is higher than the oscillation signal frequency by as much as the first frequency.

3. The semiconductor device of claim 2 , wherein the multiplier circuit includes a multiplexer configured to output the one of the third digital signal and the final test signal, the final test signal being generated from the pair of test signals to the DCO.

4. The semiconductor device of claim 1 , wherein
the LGC is further configured to receive a first parameter and a second parameter, the first parameter being used to determine frequencies of the pair of test signals, the second parameter being used to determine output durations of the pair of test signals, and
the LGC includes a controller configured to output the final test signal to the multiplier circuit, the final test signal being generated based on the first and second parameters.

5. The semiconductor device of claim 1 , wherein the LGC includes
a counter configured to
receive the oscillation signal, and
generate the pair of test signals, and

a compensation factor calculator (CFC) configured to
receive the pair of test signals, and
generate a multiplication coefficient setting signal for setting the multiplication coefficient.

6. The semiconductor device of claim 5 , wherein the CFC is further configured to
receive a third parameter used to determine a ratio of the oscillation signal frequency and a gain of the DCO, and
generate the multiplication coefficient setting signal based on the third parameter.

7. The semiconductor device of claim 1 , further comprising:
an automatic frequency calibrator (AFC) configured to calibrate the oscillation signal frequency using a binary search algorithm.

8. The semiconductor device of claim 1 , further comprising:
a controller configured to
receive a first parameter and a second parameter, the first parameter being used to determine frequencies of the pair of test signals, the second parameter being used to determine output durations of the pair of test signals, and
output the final test signal generated based on the first and second parameters.

9. A semiconductor device comprising:
a time-to-digital converter (TDC) configured to
receive a reference frequency signal and a feedback frequency signal, and
output a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal;

a digital loop filter (DLF) configured to output a second digital signal generated by filtering the first digital signal;
a multiplier circuit including
a multiplier configured to generate a third digital signal by performing a multiplication operation on the second digital signal using a multiplication coefficient, and
a multiplexer configured to selectively output one of the third digital signal and a final test signal to a digital-controlled oscillator (DCO);
the DCO configured to generate an oscillation signal having an oscillation signal frequency based on the output one of the third digital signal and the final test signal; and
an loop gain calibrator (LGC) configured to
receive the oscillation signal,
generate a pair of test signals, and
generate the final test signal using the pair of test signals.

10. The semiconductor device of claim 9 , wherein
the pair of test signals include first and second test signals,
a frequency of the first test signal is lower than the oscillation signal frequency by as much as a first frequency, and
a frequency of the second test signal is higher than the oscillation signal frequency by as much as the first frequency.

11. The semiconductor device of claim 9 , wherein the LGC is further configured to determine the multiplication coefficient using the pair of test signals.

12. The semiconductor device of claim 9 , wherein
the LGC is further configured to receive a first parameter and a second parameter, the first parameter being used to determine frequencies of the pair of test signals, the second parameter being used to determine output durations of the pair of test signals, and
the LGC includes a controller configured to output the final test signal generated based on the first and second parameters.

13. The semiconductor device of claim 9 , wherein the LGC includes
a counter configured to
receive the oscillation signal, and
generate the pair of test signals, and

a compensation factor calculator (CFC) configured to
receive the pair of test signals, and
generate a multiplication coefficient setting signal for setting the multiplication coefficient.

14. The semiconductor device of claim 13 , wherein the CFC is further configured to
receive a third parameter used to determine a ratio of the oscillation signal frequency and a gain of the DCO, and
generate the multiplication coefficient setting signal based on the third parameter.

15. The semiconductor device of claim 9 , further comprising:
an automatic frequency calibrator (AFC) configured to calibrate the oscillation signal frequency using a binary search algorithm.

16. The semiconductor device of claim 9 , further comprising:
a controller configured to
receive a first parameter and a second parameter, is the first parameter being used to determine frequencies of the pair of test signals, and the second parameter being used to determine output durations of the pair of test signals, and
output the final test signal generated based on the first and second parameters.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Won Sik
• Kim Woo Seok
• Kim Ji Hyun
• Kim Tae Ik

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title