Fast-locking all-digital phase-locked loop and applications thereof

Patent metadata

Field	Value
Publication number	US-12355452-B2
Application number	US-202218569459-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jun 14, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

First claim

The invention claimed is:

1. An all-digital phase-locked loop, ADPLL, for a radio receiver, radio transmitter or radio transceiver, the ADPLL comprising:
a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal;
a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal being either a transmission signal of the radio transmitter or transceiver or a local oscillator signal of the radio receiver or transceiver, wherein the SC-DCO comprises a variable load comprising a set of one or more parallel switchable capacitor banks and the radio frequency signal is used as the feedback signal;
a phase-locked loop controller operatively connected between the time-to-digital converter and the SC-DCO for controlling the SC-DCO based on the digital time signal received from the time-to-digital converter for achieving a phase and frequency lock; and
digital processing means communicatively connected to the phase-locked loop controller for:
maintaining, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal; and
causing the phase-locked loop controller to adjust a switching configuration of the SC-DCO for generating a radio frequency signal having a frequency of the plurality of frequencies according to the lookup table for expediting locking of the all-digital phase-locked loop.

2. The all-digital phase-locked loop of claim 1 , wherein the causing of the phase-locked loop controller to adjust the switching configuration of the SC-DCO comprises:
determining a switching configuration for the SC-DCO matching a frequency scheduled for generation by the all-digital phase-locked loop based on the lookup table, wherein the frequency is one of said plurality of frequencies and is defined in a pre-defined frequency schedule maintained in said at least one memory or by a user input communicated to the digital processing means; and
causing the phase-locked loop controller to adjust a switching configuration of the SC-DCO according to the determined switching configuration so as to generate a radio frequency signal having said frequency for expediting frequency and phase locking of the all-digital phase-locked loop,
wherein the phase-locked loop controller is configurable to operate, at a time, either in a closed-loop operating mode where the switching configuration of the SC-DCO is continuously controlled based on the digital time signal received from the time-to-digital converter for achieving a phase and frequency lock or in an open-loop operating mode where no digital time signal is receivable by the phase-locked loop controller from the time-to-digital converter, the digital processing means being further configured to cause the phase-locked loop controller to switch between the open-loop operating mode and the closed-loop operating mode.

3. The all-digital phase-locked loop according to claim 1 , wherein the digital processing means are further configured to perform:
causing the phase-locked loop controller to activate the SC-DCO before the adjusting of the switching configuration of the SC-DCO.

4. The all-digital phase-locked loop according to claim 1 , wherein the causing of the phase-locked loop controller to adjust the switching configuration of the SC-DCO is performed in response to a switch of the frequency desired to be generated by the SC-DCO.

5. The all-digital phase-locked loop according to claim 1 , wherein the digital processing means are further configured to generate the lookup table by performing the following for each of the plurality of frequencies:
determining whether a switching configuration for a first frequency of the plurality of frequencies scheduled for generation by the all-digital phase-locked loop is comprised the lookup table, wherein the first frequency is defined in a pre-defined frequency schedule maintained in said at least one memory or by a user input communicated to the digital processing means; and
in response to no switching configuration for the first frequency being available in the lookup table, waiting for the all-digital phase-locked loop to lock to the first frequency and, following the locking, receiving information on a current locked switching configuration for the first frequency from the PLL controller and storing the first frequency and the current locked switching configuration of the SC-DCO to the lookup table.

6. The all-digital phase-locked loop according to claim 1 , wherein the digital processing means comprise:
at least one processor communicatively connected to the phase-locked loop controller for controlling the phase-locked loop controller; and
said at least one memory accessible by said at least one processor and comprising program instructions executable by the at least one processor for causing the performance of the digital processing means.

7. The all-digital phase-locked loop according to claim 1 , wherein the phase-locked loop controller comprises:
a digital loop filter for generating one or more parallel digital control signals enabling the controlling of the SC-DCO; and
a register interface for communication between the digital loop filter and the digital processing means.

8. The all-digital phase-locked loop according to claim 7 , wherein the register interface is further configured to enable transmitting of activation and deactivation signals from the digital processing means to the SC-DCO.

9. The all-digital phase-locked loop of claim 7 , wherein the phase locked loop controller further comprises:
a digital 2-to-1 multiplexer for switching between open and closed loop operating modes, wherein a first input pin of the digital 2-to-1 multiplexer is connected to an output of the time-to-digital converter, a second input pin of the digital 2-to-1 multiplexer is defined to have a constant bit value, an output pin of the digital 2-to-1 multiplexer is connected to the digital loop filter and an input value of a selector pin of the digital 2-to-1 multiplexer is controllable by the digital processing means via the register interface.

10. The all-digital phase-locked loop according to claim 7 , wherein the set of one or more parallel switchable capacitor banks of the SC-DCO comprises a switchable tracking capacitor bank for frequency tracking and the phase-locked loop controller further comprises:
a sigma-delta modulator for generating a tracking signal for inputting to the SC-DCO based on a digital signal received from the digital loop filter.

11. The all-digital phase-locked loop according to claim 1 , wherein the set of one or more parallel switchable capacitor banks of the SC-DCO comprises at least a first switchable capacitor bank for coarse tuning, a second switchable capacitor bank for less coarse tuning than the first switchable capacitor bank and a switchable tracking capacitor bank for frequency tracking.

12. The all-digital phase-locked loop according to claim 1 , wherein said variable load further comprises at least one inductor connected in parallel with the set of one or more parallel switchable capacitor banks.

13. A radio device, comprising an all-digital phase-locked loop, ADPLL, for generating the local oscillator signal of the radio device, the ADPLL comprising:
a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal;
a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal being either a transmission signal of the radio transmitter

Assignees

• Nordic Semiconductor Asa

Inventors

• Wulff Carsten
• Vedal Tor Øyvind
• Bruset Ola
• Balasubramanian Shankkar
• Undheim Ruben
• Garvik Harald

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/104 Primary

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title