Backside source/drain replacement for semiconductor devices with metallization on both sides

Patent metadata

Field	Value
Publication number	US-10892337-B2
Application number	US-201616327198-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a substrate;
a transistor above the substrate and including:
a gate;
a semiconductor region above the gate;
a source region and a drain region adjacent to the semiconductor region;
first and second contacts above the source and drain regions, respectively; and
a seed layer below the source and drain regions, wherein the seed layer includes semiconductor material and has doping levels of at least 1E19 atoms per cubic centimeter (cm) less than doping levels of the source and drain regions;

at least one metallization layer below the transistor and between the transistor and the substrate; and
at least one metallization layer above the transistor.

2. The IC of claim 1 , wherein the semiconductor region includes a layer of single-crystal semiconductor material having less than 1E8 dislocation defects per square cm.

3. The IC of claim 1 , wherein the semiconductor region includes one or both of group IV semiconductor material and group III-V semiconductor material.

4. The IC of claim 1 , wherein the transistor further includes a gate dielectric layer between the gate and the semiconductor region.

5. The IC of claim 1 , wherein the source and drain regions each include an n-type dopant or a p-type dopant.

6. The IC of claim 1 , wherein the source and drain regions include semiconductor material having a doping level of greater than 1E20 atoms per cubic cm.

7. The IC of claim 1 , wherein the first and second contacts include one of a metal and a metal alloy material.

8. The IC of claim 1 , wherein the seed layer includes one or both of group IV semiconductor material and group III-V semiconductor material.

9. The IC of claim 1 , wherein the seed layer includes composite material included in the source and drain regions, but with greater concentration of at least one constituent of the composite material.

10. The IC of claim 1 , wherein the source and drain regions and the seed layer both include silicon (Si) and germanium (Ge), and wherein the seed layer includes at least 10 percent less germanium concentration than germanium concentration in the source and drain regions.

11. The IC of claim 1 , wherein the seed layer includes carbon alloying of at least 1 percent.

12. The IC of claim 1 , wherein the seed layer is undoped.

13. The IC of claim 1 , wherein the source and drain regions include third and fourth contacts below the source and drain regions, respectively, such that the seed layer is between the third and fourth contacts and the respective source and drain regions and such that the source and drain regions are contacted from two or more sides.

14. The IC of claim 1 , wherein the transistor includes one or both of a finned configuration and a nanowire configuration, and wherein the transistor is one of a p-channel metal-oxide-semiconductor field-effect transistor (p-MOS), an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS), a p-channel tunnel field-effect transistor (p-TFET), and an n-channel tunnel field-effect transistor (n-TFET).

15. An integrated circuit (IC) comprising:
a substrate;
a transistor above the substrate and including:
a gate;
a semiconductor region above the gate;
a source region and a drain region adjacent to the semiconductor region, wherein the source and drain regions include semiconductor material and have first doping levels;

first and second contacts above the source and drain regions, respectively; and
a layer below the source and drain regions, wherein the layer includes semiconductor material and has second doping levels that are less than the first doping levels;
a first interconnect layer below the transistor and between the transistor and the substrate, the first interconnect layer including dielectric material and one or more conductive interconnect features; and
a second interconnect layer above the transistor, the second interconnect layer including dielectric material and one or more conductive interconnect features.

16. The IC of claim 15 , wherein the layer below the source and drain regions includes composite material included in the source and drain regions, but with greater concentration of at least one constituent of the composite material.

17. The IC of claim 15 , wherein the source and drain regions and the layer below the source and drain regions include silicon (Si) and germanium (Ge), and wherein the layer below the source and drain regions includes at least 10 percent less germanium concentration than germanium concentration in the source and drain regions.

18. The IC of claim 15 , wherein the layer below the source and drain regions includes carbon alloying of at least 1 percent.

19. A method of forming an integrated circuit, the method comprising:
depositing a sacrificial layer on a first substrate;
forming a single-crystal semiconductor material layer on the sacrificial layer;
forming a transistor device using the semiconductor material layer, the transistor including a gate, a semiconductor region below the gate, a source region and a drain region adjacent to the semiconductor region, and a seed layer above the source and drain regions, wherein the source and drain regions include sacrificial source and drain material;
bonding a metallization layer of the first substrate to a metallization layer of a second substrate;
removing the sacrificial layer to remove the first substrate;
forming contact trenches to access a side of the source and drain regions opposite the second substrate;
selectively etching the sacrificial source and drain material without completely removing the seed layer to form source and drain trenches;
forming final source and drain material on the seed layer and in the source and drain trenches; and
forming contacts in the contact trenches.

20. The method of claim 19 , wherein selectively etching the sacrificial source and drain material includes using a given etchant that removes the sacrificial source and drain material at least 5 times faster than the given etchant removes material of the seed layer, and wherein the seed layer includes at least 1E18 atoms per cubic centimeter (cm) less dopants than the sacrificial source and drain material.

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Jambunathan Karthik
• Murthy Anand S
• Mohapatra Chandra S
• Morrow Patrick
• Kobrinsky Mauro J

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title