Semiconductor device

Patent metadata

Field	Value
Publication number	US-12563783-B2
Application number	US-202318103897-A
Country	US
Kind code	B2
Filing date	Jan 31, 2023
Priority date	Jun 13, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A semiconductor device includes first and second active patterns respectively provided on a first and second PMOSFET regions of a substrate, a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked and spaced apart from each other, a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked and spaced apart from each other, a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern. A first concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the first gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the second gate electrode.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first active pattern provided on a first PMOSFET region of a substrate and a second active pattern respectively a second PMOSFET region of the substrate; a first channel pattern on the first active pattern, the first channel pattern comprising first semiconductor patterns stacked and spaced apart from each other; a second channel pattern on the second active pattern, the second channel pattern comprising second semiconductor patterns stacked and spaced apart from each other; a first gate electrode on the first channel pattern; and a second gate electrode on the second channel pattern, wherein the first gate electrode comprises a first inner gate electrode provided in a first inner region between the first semiconductor patterns and a first outer gate electrode provided in a first outer region spaced apart from the first semiconductor patterns, wherein the second gate electrode comprises a second inner gate electrode provided in a second inner region between the second semiconductor patterns and a second outer gate electrode provided in a second outer region spaced apart from the second semiconductor patterns, and wherein a first concentration of aluminum (Al) or silicon (Si) in the first inner gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in the second inner gate electrode.

2 . The semiconductor device of claim 1 , wherein a work-function of the first inner gate electrode is different from a work-function of the second inner gate electrode.

3 . The semiconductor device of claim 1 , wherein a difference between the first concentration and the second concentration ranges from 3 at % to 25 at %.

4 . The semiconductor device of claim 1 , wherein each of the first outer gate electrode and the second outer gate electrode comprises a first metal pattern, a second metal pattern on the first metal pattern, and a fill metal pattern on the second metal pattern,
wherein the first inner gate electrode has a composition different from the first metal pattern, and wherein the second inner gate electrode and the first metal pattern have a common composition.

5 . The semiconductor device of claim 4 , wherein the first concentration is different from a concentration of aluminum (Al) or silicon (Si) in the first metal pattern.

6 . The semiconductor device of claim 4 , wherein the first metal pattern of the first outer gate electrode covers both side surfaces of the first inner gate electrode.

7 . The semiconductor device of claim 4 , wherein the first inner gate electrode has a first thickness, and
wherein the first metal pattern has a second thickness that is greater than the first thickness.

8 . The semiconductor device of claim 1 , further comprising a high-k dielectric layer interposed between the first channel pattern and the first gate electrode,
wherein the high-k dielectric layer comprises:
a first portion on a top or bottom surface of each of the first semiconductor patterns; and
a second portion on a side surface of each of the first semiconductor patterns,
wherein the first inner gate electrode covers the first portion, and wherein the first outer gate electrode covers the second portion.

9 . The semiconductor device of claim 1 , wherein one of the first semiconductor patterns comprises a first side surface,
wherein the first inner gate electrode comprises a second side surface, and wherein a recess depth of the second side surface relative to the first side surface ranges from about 2 nm to about 5 nm.

10 . The semiconductor device of claim 1 , wherein the first inner gate electrode comprises a metal nitride material, in which aluminum (Al) or silicon (Si) is absent, and
wherein the second inner gate electrode comprises a metal nitride material comprising aluminum (Al) or silicon (Si).

11 . A semiconductor device, comprising:
a substrate; a device isolation layer provided on the substrate and defining an active pattern; semiconductor patterns on the active pattern; and a gate electrode on the semiconductor patterns, wherein the gate electrode comprises an inner gate electrode and an outer gate electrode, each of which comprises inner electrodes, wherein the inner electrodes of the inner gate electrode and the semiconductor patterns are alternately stacked to define a fin structure, wherein the outer gate electrode comprises:
a first metal pattern on the fin structure;
a second metal pattern on the first metal pattern; and
a fill metal pattern on the second metal pattern, and
wherein a first concentration of aluminum (Al) or silicon (Si) in the inner gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in the first metal pattern.

12 . The semiconductor device of claim 11 , wherein a difference between the first concentration and the second concentration ranges from 3 at % to 25 at %.

13 . The semiconductor device of claim 11 , wherein the inner gate electrode comprises a metal nitride material, in which aluminum (Al) or silicon (Si) is absent, and
wherein the first metal pattern comprises a metal nitride material comprising aluminum (Al) or silicon (Si).

14 . The semiconductor device of claim 11 , wherein the semiconductor patterns comprise a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern, which are stacked on the active pattern and spaced apart from each other, and
wherein the inner gate electrode comprises a first inner electrode between the active pattern and the first semiconductor pattern, a second inner electrode between the first semiconductor pattern and the second semiconductor pattern, and a third inner electrode between the second semiconductor pattern and the third semiconductor pattern.

15 . The semiconductor device of claim 11 , further comprising a high-k dielectric layer enclosing each of the semiconductor patterns,
wherein the high-k dielectric layer comprises:
a first portion on a top or bottom surface of each of the semiconductor patterns; and
a second portion on a side surface of each of the semiconductor patterns,
wherein the inner gate electrode covers the first portion, and wherein the first metal pattern covers the second portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Jaeyeol
• Kwon Ohseong
• Bae Suyoung
• Kim Sangyong

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/668

  the layer being a silicide, e.g. TiSi2 · CPC title