Gate-all-around FETs having uniform threshold voltage

Patent metadata

Field	Value
Publication number	US-10692778-B2
Application number	US-201816051833-A
Country	US
Kind code	B2
Filing date	Aug 1, 2018
Priority date	Aug 1, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), each including an inner work function metal, an outer work function metal, a first nanosheet comprising an inner channel surface having a first threshold voltage, and a second nanosheet comprising an outer channel surface having a second threshold voltage; and
modifying the outer work function metal so as to cause the outer channel surface of the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

2. The method of claim 1 , wherein modifying the outer work function metal so as to cause the outer channel surface of the second nanosheet to have the second threshold voltage be within the predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet comprises implantation.

3. The method of claim 2 , wherein the implantation comprises implanting material in the outer work function metal, the material causing the second threshold voltage to change and become within the predefined amount of the first threshold voltage.

4. The method of claim 1 , wherein modifying the outer work function metal so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage be within the predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet comprises plasma treatment.

5. The method of claim 4 , wherein the plasma treatment comprises doping the outer work function metal with material that causes the second threshold voltage to change and become within the predefined amount of the first threshold voltage.

6. The method of claim 1 , wherein modifying the outer work function metal so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage be within the predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet comprises applying a thermal anneal.

7. The method of claim 6 , wherein the thermal anneal comprises thermally driving material into the outer work function metal, the material causing the second threshold voltage to change and become within the predefined amount of the first threshold voltage.

8. The method of claim 1 , wherein modifying the outer work function metal so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage be within the predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet comprises directional deposition.

9. The method of claim 8 , wherein the directional deposition comprises depositing material over the second nanosheet, the material causing the second threshold voltage to change and become within the predefined amount of the first threshold voltage.

10. A method of treating a gate-all-around field effect transistor, the method comprising:
providing at least one stack comprising an inner work function metal and an outer work function metal; and
modifying the outer work function metal so as to cause an outer threshold voltage of an outer channel to be within a predefined amount of an inner threshold voltage of an inner channel in the at least one stack, the predefined amount being within about 20 millivolts (mV).

11. The method of claim 10 , wherein the at least one stack comprises a first nanosheet comprising the inner channel having the inner threshold voltage and a second nanosheet comprising the outer channel surface having the outer threshold voltage.

12. The method of claim 10 , wherein modifying the outer work function metal so as to cause the outer threshold voltage of the outer channel to be within the predefined amount of the inner threshold voltage of the inner channel comprises performing a process, the process is selected from the group consisting of implantation of material in the outer work function metal, plasma treatment to dope the material in the outer work function metal, and thermal annealing to diffuse the material in the outer work function metal.

13. The method of claim 12 , wherein the at least one stack comprises a PFET and an NFET.

14. The method of claim 13 , wherein the material is different in the PFET and the NFET.

15. The method of claim 10 , wherein modifying the outer work function metal so as to cause the outer threshold voltage of the outer channel to be within the predefined amount of the inner threshold voltage of the inner channel in the at least one stack comprises directional deposition of an additional layer of material.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Guo Dechao
• Wang Junli
• Wu Heng

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6212

  having fin-shaped semiconductor bodies having non-rectangular cross-sections · CPC title