Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

Patent metadata

Field	Value
Publication number	US-10692866-B2
Application number	US-201816036067-A
Country	US
Kind code	B2
Filing date	Jul 16, 2018
Priority date	Jul 16, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate;
wherein the first fabrication operations include:
forming a first channel nanosheet;
forming a second channel nanosheet over the first channel nanosheet;
forming a first gate structure around the first channel nanosheet;
forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure; and
applying a dopant to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

2. The method of claim 1 , wherein applying the dopant comprises exposing the first gate structure and the second gate structure to a dopant carrying gas.

3. The method of claim 2 , wherein applying the dopant further comprises applying an anneal at a temperature within a range from about 350 Celsius to about 450 Celsius.

4. The method of claim 3 , wherein applying the dopant further comprising exposing the first gate structure and the second gate structure to an ambient comprising nitrogen.

5. The method of claim 4 , wherein the dopant comprises oxygen.

6. The method of claim 4 , wherein the dopant comprises fluorine.

7. The method of claim 2 , wherein:
applying the dopant further comprises applying an anneal at a temperature within a range from about 600 Celsius to about 800 Celsius; and
the dopant comprises nitrogen.

8. The method of claim 3 , wherein a threshold voltage of each of the nanosheet FET devices in the first region is controlled by:
a material type that forms the first gate structure;
a material type that forms the second gate structure;
the dopant;
a thickness dimension of the first gate structure;
a thickness dimension of the second gate structure;
a temperature of the anneal; and
a duration of the anneal.

9. The method of claim 1 further comprising:
performing second fabrication operations to form nanosheet field effect transistor (FET) devices in a second region of a substrate;
wherein the second fabrication operations include:
forming a third channel nanosheet;
forming a fourth channel nanosheet over the third channel nanosheet;
forming a third gate structure around the third channel nanosheet;
forming a fourth gate structure around the fourth channel nanosheet, wherein the third gate structure and the fourth gate structure pinch off in a pinch off area between the third gate structure and the fourth gate structure; and
applying the dopant to the third gate structure and the fourth gate structure, wherein the dopant is configured to penetrate into the gate structure and the fourth gate structure to formed a doped area of the third gate structure and a doped area of the fourth gate structure;
wherein at least a portion of the pinch off area remains undoped after applying the dopant.

10. The method of claim 9 , wherein applying the dopant comprises exposing the first gate structure, the second gate structure, the third gate structure and the fourth gate structure to the dopant carrying gas.

11. The method of claim 10 , wherein applying the dopant further comprises applying an anneal at a temperature within a range from about 350 Celsius to about 450 Celsius.

12. The method of claim 11 , wherein applying the dopant further comprising exposing the first gate structure and the second gate structure to an ambient comprising nitrogen.

13. The method of claim 12 , wherein the dopant comprises oxygen.

14. The method of claim 12 , wherein the dopant comprises fluorine.

15. The method of claim 10 , wherein:
applying the dopant further comprises applying an anneal at a temperature within a range from about 600 Celsius to about 800 Celsius; and
the dopant comprises nitrogen.

16. The method of claim 10 , wherein a threshold voltage of each of the nanosheet FET devices in the first region is controlled by:
a material type that forms the first gate structure;
a material type that forms the second gate structure;
the dopant;
a thickness dimension of the first gate structure;
a thickness dimension of the second gate structure;
a temperature of the anneal; and
a duration of the anneal.

17. The method of claim 16 , wherein a threshold voltage of each of the nanosheet FET devices in the second region is controlled by:
a material type that forms the third gate structure;
a material type that forms the fourth gate structure;
the dopant;
a thickness dimension of the third gate structure;
a thickness dimension of the fourth gate structure;
the temperature of the anneal; and
the duration of the anneal.

Assignees

• IBM

Inventors

• Ando Takashi
• Zhang Jingyun
• Lee Choonghyun
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title