Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Patent metadata

Field	Value
Publication number	US-11264289-B2
Application number	US-202016924937-A
Country	US
Kind code	B2
Filing date	Jul 9, 2020
Priority date	Jul 11, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

First claim

The invention claimed is:

1. A method of microfabrication, the method comprising:
receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other in which individual channels extend horizontally between source/drain regions, wherein for each vertical stack of channels at least one channel is positioned above a second channel, the channels including at least four designated channel types including high voltage PMOS channels, high voltage NMOS channels, low voltage PMOS channels and low voltage NMOS channels;
selectively depositing a first high-k dielectric all around uncovered channels including high voltage PMOS channels, high voltage NMOS channels, low voltage PMOS channels and low voltage NMOS channels;
selectively depositing a first work function metal on each high voltage NMOS channel and each low voltage NMOS channel while the high voltage PMOS channels and the low voltage PMOS channels are covered;
selectively depositing a second work function metal on each high voltage PMOS channel and each low voltage PMOS channel while the high voltage NMOS channels and the low voltage NMOS channels are covered;
selectively depositing a third work function metal on each high voltage PMOS channel and each high voltage NMOS channel while the low voltage PMOS channels and the low voltage NMOS channels are covered; and
depositing conductive metal material on the high voltage PMOS channels, the high voltage NMOS channels, the low voltage PMOS channels and the low voltage NMOS channels after deposition of the first, second and third work function metals.

2. The method of claim 1 , further comprising covering a portion of the high voltage NMOS channels and selectively depositing a second high-k dielectric on uncovered portions of the high voltage NMOS channels to result in different threshold voltages among the high voltage NMOS channels, wherein the second high-k dielectric is the same or a different material than the first high-k dielectric.

3. The method of claim 2 , further comprising covering a portion of the high voltage PMOS channels and selectively depositing a second high-k dielectric on uncovered portions of high voltage PMOS channels to result in different threshold voltages among the high voltage PMOS channels, wherein the second high-k dielectric is the same or a different material than the first high-k dielectric.

4. The method of claim 1 , further comprising covering a portion of the high voltage NMOS channels and selectively depositing a specific work function metal on uncovered portions of the high voltage NMOS channels to result in different threshold voltages among high voltage NMOS channels.

5. The method of claim 1 , further comprising selectively depositing a first capping material on the first high-k dielectric subsequent to depositing the first high-k dielectric.

6. The method of claim 1 , wherein depositing the first high-k dielectric all around uncovered channels includes depositing the first high-k dielectric on all sides of a cross-section of the uncovered channels without depositing the first high-k dielectric on sidewalls of a replacement gate.

7. The method of claim 1 , further comprising forming high voltage channels with different gate stack thicknesses thereby resulting in different threshold voltages among high voltage channels.

8. The method of claim 1 , further comprising forming low voltage channels with different gate stack thicknesses thereby resulting in different threshold voltages among low voltage channels.

9. The method of claim 1 , further comprising selectively depositing a first titanium nitrite (TiN) capping material on the first high-k dielectric subsequent to depositing the first high-k dielectric.

10. The method of claim 5 , further comprising annealing the vertical stacks of channels subsequent to depositing the first capping material.

11. The method of claim 9 , further comprising annealing the vertical stacks of channels subsequent to depositing the first titanium nitrite capping material.

12. The method of claim 3 , wherein covering a portion of the high voltage NMOS channels comprises patterning a filling material all around the portion of the high voltage NMOS channels, wherein the filling material is spin-on carbon.

13. The method of claim 12 , further comprising removing the filling material subsequent to selectively depositing the first high-k dielectric on the high voltage NMOS channels.

14. The method of claim 1 , further comprising:
covering the high voltage PMOS channels and the low voltage PMOS channels with a filling material prior to selectively depositing the first work function metal on each high voltage NMOS channel and each low voltage NMOS channel and removing the filling material by wet etching subsequent to selectively depositing the first work function metal on each high voltage NMOS channel and each low voltage NMOS channel;
covering the high voltage NMOS channels and the low voltage NMOS channels with the filling material prior to selectively depositing the second work function metal on each high voltage PMOS channel and each low voltage PMOS channel and removing the filling material by wet etching subsequent to selectively depositing the second work function metal on each high voltage PMOS channel and each low voltage PMOS channel; and
covering the low voltage PMOS channels and the low voltage NMOS channels with the filling material by wet etching prior to selectively depositing the third work function metal on each high voltage PMOS channel and each high voltage NMOS channel and removing the filling material subsequent to selectively depositing the third work function metal on each high voltage PMOS channel and each high voltage NMOS channel.

15. The method of claim 1 , further comprising isotropically depositing a liner material on the high voltage PMOS channels, the high voltage NMOS channels, the low voltage PMOS channels and the low voltage NMOS channels prior to depositing the conductive metal material.

16. The method of claim 1 , further comprising selectively depositing each work function metal by one of atomic layer selective deposition (ALD) or chemical vapor selective deposition (CVD).

17. The method of claim 1 , further comprising:
selecting the liner material from the group consisting of tantallum nitrate (TaN) and titanium nitrate (TiN);
selecting the conductive metal material from the group consisting of tungsten, cobalt, ruthenium, aluminum and alloys of aluminum; and
selecting the work functions metals from the group consisting of titanium nitride (TiN), titanium oxy nitride (TiON), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TiC), and aluminum doped titanium carbide (TiAlC).

18. A method of microfabrication of vertical stacks of nano-channels, each vertical stack having a different voltage threshold, the method comprising:
receiving a substrate having channels for gate-all-around field-effect transistor devices, the channels including vertical stacks of nano-channels positioned adjacent to each other in which individual nano-channels extend horizontally between source/drain regions, wherein for each vertical stack of channels at least one nano-channel is positioned above a second nano-channel, the nano-channels including at least four designated nano-channel types including high voltage PMOS nano-channels, high voltage NMOS nano-channels, low voltage PMOS nano-channels and low voltage NMOS nano-channels;
depositing a high-k film ov

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Tapily Kandabara
• Liebmann Lars
• Chanemougame Daniel
• Gardner Mark
• Fulford H Jim
• Devilliers Anton J

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177 Primary

  the gate conductors having different materials or different implants · CPC title