Memory device and memory apparatus comprising the same

Patent metadata

Field	Value
Publication number	US-12563744-B2
Application number	US-202318164926-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	Aug 31, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Disclosed are a memory device and a memory apparatus including the memory device. The memory device may include a first electrode, a second electrode spaced apart from the first electrode, an intermediate layer between the first electrode and the second electrode, and an interface layer in contact with the intermediate layer. The intermediate layer and the interface layer each may have ovonic threshold switching (OTS) characteristics. A material of the interface layer may have a threshold voltage shift greater than a threshold voltage shift (ΔVth) of the intermediate layer.

First claim

What is claimed is:

1 . A memory device comprising:
a first electrode; a second electrode spaced apart from the first electrode; an intermediate layer between the first electrode and the second electrode, the intermediate layer having ovonic threshold switching characteristics; and an interface layer in contact with the intermediate layer, the interface layer having ovonic threshold switching characteristics, wherein a material of the interface layer has a polarity-induced threshold voltage shift greater than a polarity-induced threshold voltage shift of the intermediate layer.

2 . The memory device of claim 1 , wherein a threshold voltage change rate of the intermediate layer is less than a threshold voltage change rate of the interface layer.

3 . The memory device of claim 1 , wherein a threshold voltage change rate of the intermediate layer is 60 mV/dec or less.

4 . The memory device of claim 1 , wherein the intermediate layer and the interface layer each include a chalcogen compound.

5 . The memory device of claim 1 , wherein the intermediate layer includes at least one of GeAsSeIn, GeAsSeSIn, GeAsTeSi, and GeAsSeTeSi.

6 . The memory device of claim 1 , wherein the interface layer includes GeAsSe.

7 . The memory device of claim 1 , wherein a ratio of germanium (Ge) in the interface layer is greater than a ratio of Ge in the intermediate layer.

8 . The memory device of claim 7 , wherein the ratio of Ge in the interface layer is 20% or more.

9 . The memory device of claim 7 , wherein the ratio of Ge in the intermediate layer is less than 20%.

10 . The memory device of claim 1 , wherein the intermediate layer is doped with a metal.

11 . The memory device of claim 10 , wherein a doping ratio of the metal is 5% or less.

12 . The memory device of claim 10 , wherein the metal includes at least one of indium (In), aluminum (Al), silicon (Si), and gallium (Ga).

13 . The memory device of claim 1 , wherein a metal doping ratio of the interface layer is less than a metal doping ratio of the intermediate layer.

14 . The memory device of claim 1 , wherein the interface layer is not doped with a metal.

15 . The memory device of claim 1 , wherein the interface layer is between the first electrode and the intermediate layer.

16 . The memory device of claim 1 , wherein the interface layer is between the second electrode and the intermediate layer.

17 . The memory device of claim 1 , wherein
the interface layer comprises a first interface layer and a second interface layer, the first interface layer is between the first electrode and the intermediate layer; and the second interface layer is between the second electrode and the intermediate layer.

18 . A memory apparatus comprising:
a first electrode line extending in a first direction; a second electrode line spaced apart from the first electrode line and extending in a second direction crossing the first direction; and a memory device according to claim 1 at an intersection of the first electrode line and the second electrode line.

19 . The memory apparatus of claim 18 , wherein
the first electrode is in contact with the first electrode line, and the second electrode is in contact with the second electrode line.

20 . The memory apparatus of claim 18 , wherein
the first electrode is integrated with the first electrode line, and the second electrode is integrated with the second electrode line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Kiyeon
• Koo Bonwon
• Sung Hajun
• Lee Changseung
• Choi Minwoo

Classifications

• H10N70/841

  Electrodes · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/882 Primary

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title