Electronic device including memory cells having variable resistance characteristics

Patent metadata

Field	Value
Publication number	US-9305976-B2
Application number	US-201414540710-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Aug 19, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An electronic device includes a semiconductor memory. The semiconductor memory includes a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; and a selection element layer disposed over at least a part of a sidewall of the stack structure.

First claim

What is claimed is:

1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising:
a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; and
a selection element layer disposed over at least a part of a sidewall of the stack structure so that the selection element layer selectively couples the first electrode and the second electrode.

2. The electronic device according to claim 1 , wherein the selection element layer includes any one of an OTS (Ovonic Threshold Switching) material layer, an MIEC (Mixed Ionic Electronic Conducting) material layer, an MIT (Metal Insulator Transition) material layer, and a tunneling insulating layer.

3. The electronic device according to claim 1 , wherein the selection element layer has a band gap smaller than that of the insulating layer.

4. The electronic device according to claim 1 , wherein the selection element layer switches between an insulating state and a conductive state according to a level of a voltage or current applied to the selection element layer.

5. The electronic device according to claim 1 , wherein the selection element layer includes an operating portion and a remaining portion,
wherein the operating portion of the selection element layer is adjacent to the insulating layer and selectively couples the first electrode and the second electrode, and
wherein the operating portion has a resistance state different from that of the remaining portion of the selection element layer when a voltage equal to or higher than a threshold voltage is applied to the selection element layer.

6. The electronic device according to claim 5 , wherein the operating portion of the selection element layer is spaced apart from an outer wall of the selection element layer such that the operating portion does not include a portion damaged by an etching process.

7. The electronic device according to claim 1 , wherein a resistance switching operation of the variable resistance layer is performed in a part of the variable resistance layer.

8. The electronic device according to claim 1 , wherein a conductive filament electrically connecting the second electrode and the third electrode is generated in an inner portion of the variable resistance layer, and
wherein the inner portion of the variable resistance layer is sufficiently spaced apart from the sidewall of the stack structure so that the inner portion does not include a portion damaged by an etching process.

9. The electronic device according to claim 1 , wherein the semiconductor memory unit comprises a plurality of memory cells each of which includes the stack structure and the selection element layer.

10. The electronic device according to claim 9 , wherein the semiconductor memory unit further comprises:
first lines extending in a first direction; and
second lines extending in a second direction crossing the first direction, and
wherein the plurality of memory cells are disposed at intersections of the first lines and the second lines and interposed between the first lines and the second lines.

11. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory unit is a part of the memory unit in the microprocessor.

12. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory unit is a part of the cache memory unit in the processor.

13. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory unit is a part of the auxiliary memory device or the main memory device in the processing system.

14. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory unit is a part of the storage device or the temporary storage device in the data storage system.

15. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory unit is a part of the memory or the buffer memory in the memory system.

16. The electronic device according to claim 1 , wherein a cross-section of the selection element layer has a sidewall spacer shape.

17. The electronic device according to claim 1 , wherein the selection element layer is disposed over sidewalls of the first electrode, the insulating layer and the second electrode.

18. The electronic device according to claim 1 , wherein the stack structure corresponds to a first stack structure, the device further comprising:
a second stack structure that has substantially the same configuration as the fi

Assignees

• Sk Hynix Inc

Inventors

• Cho Kwang-Hee

Classifications

• H01L45/08

  Electricity · mapped topic

• G06F2212/60

  Details of cache memory · CPC title

• G06F12/084

  with a shared cache · CPC title

• H01L27/2481 Primary

  Electricity · mapped topic

• G06F13/1673

  using buffers · CPC title