Semiconductor device having stacked transistor pairs and method of forming same

Patent metadata

Field	Value
Publication number	US-11244949-B2
Application number	US-201916441725-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Jun 15, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first and second sets of transistors arranged on a substrate, each set comprising a pass transistor and a stacked complementary transistor pair including a lower transistor and an upper transistor,
wherein each transistor of the first set comprises a semiconductor channel extending between respective source and drain regions along a horizontal first fin track, and each transistor of the second set comprises a semiconductor channel extending between respective source and drain regions along a second fin track parallel to the first fin track, and
wherein the semiconductor channels of the pass transistors and the semiconductor channels of the lower transistors are arranged at a first level vertically above the substrate and the semiconductor channels of the upper transistors are arranged at a second level vertically above the first level;
a first tall gate electrode forming a common gate for the semiconductor channels of the first complementary transistor pair and arranged along a horizontal first gate track transverse to the first and second fin tracks;
a first short gate electrode having a shorter height relative to the first tall gate electrode and forming a gate for the semiconductor channel of the first pass transistor and arranged along a second gate track parallel to the first gate track;
a second tall gate electrode forming a common gate for the semiconductor channels of the second complementary transistor pair and arranged along the second gate track;
a second short gate electrode having a shorter height relative to the second tall gate electrode and forming a gate for the semiconductor channel of the second pass transistor and arranged along the first gate track;
first and second contact arrangements arranged between the first and second gate tracks and forming a common drain contact for the transistors of the first set and the second set, respectively;
a first cross-couple contact extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement; and
a second cross-couple contact extending horizontally between and interconnecting the second tall gate electrode and the first contact arrangement.

2. The semiconductor device according to claim 1 , wherein the first cross-couple contact comprises a first end in contact with the first tall gate electrode at a first interface, a second end in contact with the second contact arrangement at a second interface, and a body extending from the first interface to the second interface in a horizontal path.

3. The semiconductor device according to claim 2 , wherein the horizontal path runs above the second short gate electrode.

4. The semiconductor device according to claim 1 , wherein the second cross-couple contact comprises a first end in contact with the second tall gate electrode at a first interface, a second end arranged in contact with the first contact arrangement at a second interface, and a body extending from the first interface to the second interface in a horizontal path.

5. The semiconductor device according to claim 1 , wherein the first tall gate electrode and the second short gate electrode are arranged between a first pair of gate trench spacers extending on opposite sides of and along the first gate track, wherein the first cross-couple contact extends through the sidewall spacer of said pair which is arranged between the first gate track and the second contact arrangement.

6. The semiconductor device according to claim 1 , wherein the second tall gate electrode and the first short gate electrode are arranged between a second pair of dielectric sidewall spacers extending on opposite sides of and along the second gate track, wherein the second cross-couple contact extends through the sidewall spacer of the pair which is arranged between the second gate track and the first contact arrangement.

7. The semiconductor device according to claim 1 , wherein an upper surface of each of the first and second short gate electrodes is arranged at a third level below said second level.

8. A method of forming a semiconductor device, the method comprising:
forming first and second sets of transistors on a substrate along a horizontal first fin track and a second fin track parallel to the first fin track, respectively, each set comprising a pass transistor and a stacked complementary transistor pair including a lower transistor and an upper transistor,
wherein forming the stacked complementary transistor pair of the first set comprises forming a lower semiconductor channel at a first level above the substrate and an upper semiconductor channel at a second level above the first level, the lower and upper semiconductor channels extending between respective source and drain regions along the first fin track, and forming a first tall gate electrode along a horizontal first gate track transverse to the first and second fin tracks, the first tall gate electrode forming a common gate for the upper and lower semiconductor channels,
wherein forming the pass transistor of the first set comprises forming a first pass transistor semiconductor channel at the first level, the first pass transistor semiconductor channel extending between a source region and a drain region along the first fin track, and forming a first short gate electrode along a second gate track parallel to the first gate track, the first short gate electrode having a shorter height relative to the first tall gate electrode and forming a gate for the first pass transistor semiconductor channel,
wherein forming the stacked complementary transistor pair of the second set comprises forming a lower semiconductor channel at the first level and an upper semiconductor channel at the second level, the lower and upper semiconductor channels extending between respective source and drain regions along the second fin track, and forming a second tall gate electrode along the second gate track, the second tall gate electrode forming a common gate for the upper and lower semiconductor channels, and
wherein forming the pass transistor of the second set comprises forming a second pass transistor semiconductor channel at the first level, the second pass transistor semiconductor channel extending between a source region and a drain region along the second fin track, and forming a second short gate electrode along the first gate track, the second short gate electrode having a shorter height relative to the second tall gate electrode and forming a gate for the second pass transistor semiconductor channel;
forming first and second contact arrangements along a contact track extending parallel to and between the first and second gate tracks, the first and second contact arrangements forming a common drain contact for the transistors of the first set and the transistors of the second set, respectively;
forming a first cross-couple contact extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement; and
forming a second cross-couple contact extending horizontally between and interconnecting the second tall gate electrode and the first contact arrangement.

9. The method according to claim 8 ,
wherein, subsequent to forming the first and second contact arrangements along the contact track, covering the first and second contact arrangements with a contact insulating layer, and wherein, subsequent to forming the gate electrodes along the first and second gate tracks, covering the gate electrodes with a gate insulating layer, and
wherein forming the first and second cross-couple contacts comprises:
forming a first cross-couple contact trench and a second cross-couple contact trench extending horizo

Assignees

• Imec Vzw

Inventors

• Weckx Pieter
• Boemmels Juergen
• Ryckaert Julien

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title