Structure and method for a SRAM circuit

Patent metadata

Field	Value
Publication number	US-9870815-B2
Application number	US-201615362394-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Mar 10, 2010
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack.

First claim

What is claimed is:

1. A device comprising:
a first static random access memory (SRAM) cell having a first cell size, the first SRAM cell includes a first group of field effect transistors each having a first gate stack; and
a second SRAM cell having a second cell size greater than the first cell size, wherein the second SRAM cell includes a second group of field effect transistors each having a second gate stack different from the first gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.

2. The device of claim 1 , wherein the second gate stack is different from the first gate stack in gate electrode material.

3. The device of claim 1 , wherein the second gate stack is different from the first gate stack in gate dielectric material.

4. The device of claim 1 , wherein the second group of field effect transistors includes a greater number of transistors than the first group of field effect transistors.

5. The device of claim 1 , wherein the first SRAM cell has a first alpha ratio ranging between 0.8 and 1.3 and the second SRAM cell has a second alpha ratio ranging between 0.2 and 0.6.

6. The device of claim 1 , wherein one the field effect transistors from the first group of field effect transistors has a first threshold voltage and wherein one of the field effect transistors from the second group of field effect transistors has a second threshold voltage that is different than the first threshold voltage.

7. The device of claim 1 , wherein the second group of field effect transistors includes more pull-down transistors than the first group of field effect transistors.

8. A device comprising:
a first static random access memory (SRAM) cell having:
a first two pull-down devices that are part of a first two cross-coupled inverters for data storage, and
a first two pass-gate devices configured with the first two cross-coupled inverters to form first ports for data access; and

a second SRAM cell having:
a second two pull-down devices that are part of a second two cross-coupled inverters for data storage; and
a second two pass-gate devices configured with the second two cross-coupled inverters to form second ports for data access, and

wherein the first SRAM cell includes a first number of field effect transistors and the second SRAM cell includes a second number of field effect transistors that is different than the first number of field effect transistors, and
wherein one of the field effect transistors of the first SRAM cell has a first gate stack and one of the field effect transistors of the second SRAM cell has a second gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.

9. The device of claim 8 , wherein the second two pull-down devices includes a greater number of transistors than the first two pull-down devices.

10. The device of claim 8 , wherein the first SRAM cell further includes a first two pull-up devices that are configured with the first two pull-down devices to form the first two cross-coupled inverters, and
wherein the second SRAM cell further includes a second two pull-up devices that are configured with the second two pull-down devices to form the second two cross-coupled inverters.

11. The device of claim 10 , wherein the first two pull-up devices includes a first number of transistors and the second two pull-up devices includes a second number of transistors, wherein the first number of transistors is equal to the second number of transistors.

12. The device of claim 10 , wherein each of the first two pull-up devices includes only a single transistor and wherein each of the second two pull-up devices includes only a single transistor.

13. The device of claim 10 , further comprising a write assist circuitry coupled with the first SRAM cell and operable to provide a dual level voltage to sources associated with the first two pull-up devices.

14. The device of claim 8 , wherein the first gate stack is disposed over a first channel region having a first doping concentration and the second gate stack disposed over a second channel region having a second doping concentration that is different such that the first gate stack has a first threshold voltage and the second gate stack has a second threshold voltage that is different than the first threshold voltage.

15. A device comprising:
a first static random access memory (SRAM) cell having a first cell size, the first SRAM cell includes a first group of fin field effect transistors (FinFETs) each having a first gate stack; and
a second SRAM cell having a second cell size greater than the first cell size, wherein the second SRAM cell includes a second group of FinFETs each having a second gate stack different from the first gate stack, wherein the second gate stack is different from the first gate stack in at least one of gate electrode material and gate dielectric material.

16. The device of claim 15 , wherein the second gate stack is different from the first gate stack in both gate electrode material and gate dielectric material.

17. The device of claim 15 , wherein first group of FinFETs includes n-type FinFETs, and
wherein second group of FinFETs includes n-type FinFETs.

18. The device of claim 15 , wherein the second group of FinFETs includes more pull-down transistors than the first group of FinFETs.

19. The device of claim 15 , wherein the first SRAM cell includes:
first pull-down devices that are part of a first number of cross-coupled inverters for data storage, and
first pass-gate devices configured with the first number of cross-coupled inverters to form first ports for data access, and wherein the second SRAM cell includes:
second pull-down devices that are part of a second number of cross-coupled inverters for data storage; and
second pass-gate devices configured with the second number of cross-coupled inverters to form second ports for data access.

20. The device of claim 19 , wherein the second SRAM cell includes more transistors than the first SRAM cell.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D86/215

  comprising FinFETs · CPC title