Providing orthogonal subarrays in a dynamic random access memory

Patent metadata

Field	Value
Publication number	US-12562215-B2
Application number	US-202217708448-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Mar 30, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a first subarray having a first plurality of memory cells, the first subarray having a first orientation of bitlines and wordlines; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation of bitlines and wordlines, the second orientation orthogonal to the first orientation.

2 . The apparatus of claim 1 , wherein the first subarray having the first orientation comprises:
a first plurality of bitlines adapted in a first direction; and a first plurality of wordlines adapted in a second direction orthogonal to the first direction.

3 . The apparatus of claim 2 , wherein the second subarray having the second orientation orthogonal to the first orientation comprises:
a second plurality of bitlines adapted in the second direction; and a second plurality of wordlines adapted in the first direction.

4 . The apparatus of claim 3 , wherein:
the first subarray is associated with a row decoder adapted in the first direction and a row buffer adapted in the second direction; and the second subarray is associated with a row decoder adapted in the second direction and a row buffer adapted in the first direction.

5 . The apparatus of claim 1 , wherein the second subarray is to store a lookup table (LUT) comprising tag information and, in response to a hit in the LUT of at least a portion of an address of a read request, a charge sharing operation is to occur in another subarray to enable data at the address to be read from the another subarray.

6 . The apparatus of claim 5 , wherein in response to a miss in the LUT of at least the portion of the address, the charge sharing operation does not occur.

7 . The apparatus of claim 1 , wherein the apparatus comprises a memory die having a complementary metal oxide semiconductor (CMOS) layer comprising a computation circuit, wherein a first portion of the computation circuit is adapted on the CMOS layer in association with the first subarray and the second subarray.

8 . The apparatus of claim 7 , wherein the first portion of the computation circuit is to perform a matrix multiplication between row data obtained from the first subarray and column data obtained from the second subarray.

9 . The apparatus of claim 1 , further comprising:
a third subarray having a third plurality of memory cells, the third subarray having the first orientation.

10 . The apparatus of claim 9 , wherein the first subarray comprises a source subarray, the second subarray comprises a lookup table (LUT) subarray, and the third subarray comprises a destination subarray, and wherein the second subarray is associated with a second row buffer and the third subarray is associated with a third row decoder, wherein the second row buffer and the third row decoder have a common orientation.

11 . The apparatus of claim 10 , wherein the second row buffer is directly coupled to the third row decoder, wherein the second row buffer is to provide address information to the third row decoder to enable the third row decoder to access the third subarray.

12 . The apparatus of claim 1 , wherein a latency to read information from the second subarray is less than a latency to read information from the first subarray.

13 . A method comprising:
receiving, in a memory, a read request having an address; accessing a first subarray of the memory using at least a portion of the address, the first subarray having a first orientation, to determine whether the at least portion of the address is a hit in the first subarray; and in response to the hit in the first subarray, precharging a second subarray having a second orientation and reading data from the address in the second subarray.

14 . The method of claim 13 , further comprising, in response to a miss in the first subarray, sending the read request to a storage without precharging the second subarray.

15 . The method of claim 13 , further comprising in response to the hit in the first subarray, providing information from a row buffer of the first subarray to a row decoder of the second subarray.

16 . The method of claim 13 , further comprising:
receiving, in the memory, a matrix multiplication request; accessing a first operand stored in a third subarray of the memory, the third subarray having the first orientation, the first operand comprising row data of a first matrix; accessing a second operand stored in a fourth subarray of the memory, the fourth subarray having the second orientation, the second operand comprising column data of a second matrix; and sending the first operand and the second operand to a computation circuit, to cause the computation circuit to perform a matrix multiplication between the first operand and the second operand.

17 . The method of claim 16 , further comprising sending the first operand and the second operand from at least one memory layer of a memory die to a complementary metal oxide semiconductor (CMOS) layer of the memory die, the CMOS layer comprising the computation circuit.

18 . A package comprising:
a first die comprising a central processing unit (CPU); and a second die comprising a memory, wherein the first die is adapted on the second die, the memory comprising:
a first subarray having a first plurality of memory cells, the first subarray having a first orientation and associated with a first row decoder and a first row buffer; and
a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation, the second subarray associated with a second row decoder and a second row buffer, wherein the first row buffer is to provide information from the first subarray directly to the second row decoder.

19 . The package of claim 18 , wherein the first subarray is configured to store a table, wherein in response to a read request having an address, at least a portion of which is a hit in the first subarray, the memory is to precharge the second subarray to effect a read operation for the read request.

20 . The package of claim 18 , wherein the second die further comprises a complementary metal oxide semiconductor (CMOS) layer comprising a computation circuit, wherein in response to a matrix multiplication request, the computation circuit is to perform a matrix multiplication between:
a first operand obtained from the first subarray, the first operand comprising row data of a first matrix; and a second operand obtained from the second subarray, the second operand comprising column data of a second matrix.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek Anil
• Suthram Sagar
• Koduri Rajabali
• Ranade Pushkar
• Gomes Wilfred

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title