Systems and methods for adaptive self-referenced reads of memory devices

Patent metadata

Field	Value
Publication number	US-11538522-B1
Application number	US-202117364067-A
Country	US
Kind code	B1
Filing date	Jun 30, 2021
Priority date	Jun 30, 2021
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
receive a read request for data;
apply a first voltage to the memory array based on the read request, wherein a first set of memory cells of the plurality of memory cells is configured to be read as storing a first logic value based on the first voltage;
count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
apply a second voltage to the memory array based on the total number, wherein a second set of memory cells included in the plurality of memory cells is configured to be read as storing the first logic value based on the second voltage; and
return the data based at least on bits stored in the first and the second set of memory cells.

2. The memory device of claim 1 , wherein the control circuit is configured to apply the second voltage by determining if the total number is inside of an approach zone of values or a final step zone of values.

3. The memory device of claim 2 , wherein the control circuit is configured to use a lookup table (LUT) in determining if the total number is inside of the approach range of values or the final step range of values.

4. The memory device of claim 2 , wherein the control circuit is configured to apply one or more voltage steps if the total number is inside of the approach range of values and apply a single voltage step if the total number is inside of the final step range of values.

5. The memory device of claim 2 , wherein the approach range of values, the final step range of values, or a combination thereof, are divided into one or more statistical areas.

6. The memory device of claim 5 , wherein the one or more statistical areas comprise a 1 sigma, a 2 sigma, a 3 sigma, a 4 sigma, a 5 sigma, a 6 sigma, or a combination thereof.

7. The device of claim 1 , wherein the control circuit is configured to apply the first voltage for a first time duration and to apply the second voltage for a second time duration, and wherein the first time duration is different than the second time duration.

8. The device of claim 1 , wherein the bits comprise encoded data having a weight range of between 40% and 70%.

9. The device of claim 1 , wherein the first logic value comprises a logic 1.

10. The memory device of claim 1 , wherein the first and the second voltages are included in a voltage staircase shape.

11. A method, comprising:
receiving, at a control circuit included in a memory device, a read request for data;
applying a first voltage to a memory array of the memory device based on the read request, wherein a first set of memory cells of a plurality of memory cells of the memory array is configured to be read as storing a first logic value based on the first voltage;
counting a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
applying a second voltage to the memory array based on the total number, wherein a second set of memory cells of the plurality of memory cells is configured to be read as storing the first logic value based on the second voltage; and
returning the data based at least on bits stored in the first and the second set of memory cells.

12. The method of claim 11 , wherein applying the second voltage comprises determining if the total number is inside of an approach range of values or a final step range of values, and wherein the approach range of values, the final step range of values, or a combination thereof, are divided into one or more statistical areas.

13. The method of claim 12 , comprising executing one or more voltage steps if the total number is inside of the approach range of values and executing a single voltage step if the total number is inside of the final step range of values.

14. The method of claim 11 , comprising encoding the data as encoded data and storing the encoded data in the memory array before receiving the read request, and wherein returning the data comprises decoding the encoded data.

15. The method of claim 11 , wherein applying the first voltage comprises applying the first voltage for a first time duration and wherein applying the second voltage comprises applying the second voltage for a second time duration, and wherein the first time duration is different than the second time duration.

16. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
receive a read request for data;
apply a first voltage to the memory array based on the read request, wherein a first set of memory cells of the plurality of memory cells is configured to be read as storing a first logic value based on the first voltage;
count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
determine if the total number is inside of an approach range of values, a final step range of values, or a combination thereof; and
apply one or more voltage steps if the total number is inside of the approach range of values and apply a single voltage step if the total number is inside of the final step range of values to return the data.

17. The memory device of claim 16 , wherein the approach range of values, the final step range of values, or a combination thereof, are divided into one or more statistical areas comprising a 1 sigma, a 2 sigma, a 3 sigma, a 4 sigma, a 5 sigma, a 6 sigma, or a combination thereof.

18. The memory device of claim 17 , wherein the approach range of values is divided into a first statistical area comprising the 2 sigma, the 3 sigma, or a combination thereof, and wherein the final step range of values is divided into a second statistical area comprising the 1 sigma, the 4 sigma, the 5 sigma, the 6 sigma, or a combination thereof.

19. The memory device of claim 16 , wherein the control circuit is configured to use a lookup table (LUT) in determining if the total number is inside of the approach range of values or the final step range of values.

20. The memory device of claim 16 , wherein the control circuit is configured to encode the data as encoded data having a weight between 40% and 70% and to store the encoded data in the memory array before receiving the read request, and wherein the control circuit is configured to return the data by decoding the encoded data.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Villa Corrado

Classifications

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title