Display apparatus

Patent metadata

Field	Value
Publication number	US-12557501-B2
Application number	US-202418915290-A
Country	US
Kind code	B2
Filing date	Oct 14, 2024
Priority date	Jun 18, 2020
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A display apparatus includes: a first pixel circuit on the substrate and including a first driving thin-film transistor and a first storage capacitor electrically connected to the first driving thin-film transistor; a second pixel circuit adjacent to the first pixel circuit and including a second driving thin-film transistor and a second storage capacitor electrically connected to the second driving thin-film transistor; a first initialization voltage line electrically connected to the first pixel circuit and the second pixel circuit; a second initialization voltage line electrically connected to the first initialization voltage line; and a driving voltage line between the first pixel circuit and the second pixel circuit, wherein a channel area of the first driving thin-film transistor or a channel area of the second driving thin-film transistor is between the second initialization voltage line and the driving voltage line.

First claim

What is claimed is:

1 . A display apparatus comprising:
a substrate having a display area and a non-display area outside the display area, the display area being an area where a plurality of light-emitting diodes is arranged; a plurality of pixel circuits in the display area, each of the plurality of pixel circuits including a driving thin-film transistor and a storage capacitor electrically connected to the driving thin-film transistor; a first initialization voltage line electrically connected to the plurality of pixel circuits and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction and crossing over the first initialization voltage line in the display area to form a mesh structure, the mesh structure overlapping the display area when viewed in a plan view; and a driving voltage line extending in the second direction, wherein the driving voltage line is arranged between two neighboring pixel circuits from among the plurality of pixel circuits in the plan view, and the second initialization voltage line is arranged between other two neighboring pixel circuits from among the plurality of pixel circuits in the plan view.

2 . The display apparatus of claim 1 , wherein the second initialization voltage line comprises a plurality of second initialization voltage lines, and at least two pixel circuits are arranged between two adjacent lines from among the plurality of second initialization voltage lines in the plan view.

3 . The display apparatus of claim 1 , wherein two neighboring pixel circuits from among the plurality of pixel circuits are asymmetric with respect to a virtual axis crossing between them.

4 . The display apparatus of claim 1 , wherein the second initialization voltage line and the driving voltage line Include same materials and are simultaneously formed in one process.

5 . The display apparatus of claim 1 , wherein each of the plurality of pixel circuits further includes an operation control thin-film transistor electrically connected to the driving voltage line,
wherein a semiconductor layer of the operation control thin-film transistor in a first pixel circuit from among the plurality of pixel circuits is connected to the driving voltage line through a first connection electrode, and wherein a semiconductor layer of the operation control thin-film transistor in a second pixel circuit from among the plurality of pixel circuits is directly connected to the driving voltage line.

6 . The display apparatus of claim 5 , wherein the first connection electrode includes:
a 1-1 st connection electrode corresponding to a portion of one of electrodes of the storage capacitor and contacting the driving voltage line; and a 1-2 nd connection electrode contacting the 1-1 st connection electrode and the semiconductor layer of the operation control thin-film transistor in the first pixel circuit.

7 . The display apparatus of claim 5 , wherein each of the plurality of pixel circuits further includes a compensation thin-film transistor electrically connected to the driving thin-film transistor, and
wherein a portion of a semiconductor layer of the compensation thin-film transistor in the first pixel circuit overlaps a shield electrode electrically connected to the driving voltage line.

8 . The display apparatus of claim 7 , wherein a portion of a semiconductor layer of the compensation thin-film transistor in the second pixel circuit overlaps a shield electrode electrically connected to the second initialization voltage line.

9 . The display apparatus of claim 1 , wherein the second initialization voltage line is in a same layer as the driving voltage line.

10 . The display apparatus of claim 1 , wherein the second initialization voltage line is in a layer above the first initialization voltage line.

11 . The display apparatus of claim 10 , wherein the second initialization voltage line is electrically connected to the first initialization voltage line through a second connection electrode being integral with the second initialization voltage line.

12 . The display apparatus of claim 11 , wherein each of the plurality of pixel circuits further includes an initialization thin-film transistor electrically connected to the first initialization voltage line, and
wherein the second connection electrode includes:
a 2-1 st connection electrode overlapping a portion of the first initialization voltage line and electrically connecting the first initialization voltage line with the second initialization voltage line; and
a 2-2 nd connection electrode extending from the 2-1 st connection electrode and electrically connecting the first initialization voltage line with a semiconductor layer of the initialization thin-film transistor.

13 . A display apparatus comprising:
a substrate having a display area and a non-display area outside the display area, the display area being an area where a plurality of light-emitting diodes is arranged; a second pixel circuit adjacent to a first pixel circuit and including a second driving thin-film transistor and a second storage capacitor electrically connected to the second driving thin-film transistor; a plurality of pixel circuits in the display area, each of the plurality of pixel circuits including a driving thin-film transistor and a storage capacitor electrically connected to the driving thin-film transistor; a first initialization voltage line electrically connected to the plurality of pixel circuits and extending in a first direction; a second initialization voltage line electrically connected to the first initialization voltage line and extending in a second direction crossing the first direction and crossing over the first initialization voltage line in the display area to form a mesh structure, the mesh structure overlapping the display area when viewed in a plan view; and a driving voltage line extending in the second direction between two neighboring pixel circuits from among the plurality of pixel circuits in the plan view, wherein the second initialization voltage line overlaps the driving voltage line when viewing the substrate in the plan view.

14 . The display apparatus of claim 13 , wherein the second initialization voltage line comprises a plurality of second initialization voltage lines, and at least two pixel circuits are arranged between two adjacent lines from among the plurality of second initialization voltage lines in the plan view.

15 . The display apparatus of claim 13 , wherein the two neighboring pixel circuits, with the driving voltage line arranged between them, from among the plurality of pixel circuits are symmetric with respect to a virtual axis crossing between them.

16 . The display apparatus of claim 13 , wherein each of the plurality of pixel circuits further includes an operation control thin-film transistor electrically connected to the driving voltage line, and
wherein a portion of a semiconductor layer of a compensation thin-film transistor overlaps a shield electrode electrically connected to the driving voltage line.

17 . The display apparatus of claim 13 , wherein the driving voltage line is in a layer above the first initialization voltage line, and
wherein the second initialization voltage line is in a layer above the driving voltage line.

18 . The display apparatus of claim 17 , wherein the first initialization voltage line and the second initialization voltage line are electric

Assignees

• Samsung Display Co Ltd

Inventors

• Um Nuree
• Kim Mihae
• Kim Minjeong
• Park Hyungjun
• An Junyong

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title