Organic light-emitting diode display

US9748321B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9748321-B2
Application numberUS-201615190101-A
CountryUS
Kind codeB2
Filing dateJun 22, 2016
Priority dateJul 28, 2015
Publication dateAug 29, 2017
Grant dateAug 29, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate that includes a first sub-pixel region and a second sub-pixel region adjacent to the first sub-pixel region, and a first driving circuit and a second driving circuit respectively disposed in the first sub-pixel region and the second sub-pixel region. The first and second driving circuits include a first thin film transistor (TFT) and a second TFT. The display further includes a first pixel electrode and a second pixel electrode electrically connected to the first driving circuit and the second driving circuit, respectively, and a common electrode facing the first and second pixel electrodes. A first organic emission layer is interposed between the first pixel electrode and the common electrode, and a second organic emission layer interposed between the second pixel electrode and the common electrode, and a light-shielding member is configured to shield incident light.

First claim

Opening claim text (preview).

What is claimed is: 1. An organic light-emitting diode (OLED) display, comprising: a substrate comprising a first sub-pixel region and a second sub-pixel region; a first driving circuit disposed in the first sub-pixel region and comprising a first thin film transistor (TFT) including i) a first active pattern comprising a first source region, a first channel region, and a first drain region and ii) a first gate electrode insulated from the first active pattern; a second driving circuit disposed in the second sub-pixel region and comprising a second TFT including i) a second active pattern comprising a second source region, a second channel region, and a second drain region and ii) a second gate electrode insulated from the second active pattern; a first pixel electrode and a second pixel electrode electrically connected to the first driving circuit and the second driving circuit, respectively; a common electrode facing the first and second pixel electrodes; and a light-shielding member shield incident light, wherein the light-shielding member is disposed on the second TFT, wherein at least a portion of the first pixel electrode overlaps at least one of the first source region and the first drain region in the depth dimension of the OLED display, and wherein at least a portion of the light-shielding member overlaps at least one of the second source region and the second drain region in the depth dimension of the OLED display. 2. The OLED display of claim 1 , wherein the light-shielding member and the second pixel electrode are disposed on the same layer, and wherein the light-shielding member is spaced apart from the second pixel electrode. 3. The OLED display of claim 1 , wherein the light-shielding member extends from a third pixel electrode different from the first and second pixel electrodes and adjacent to the second sub-pixel region. 4. The OLED display of claim 1 , wherein the second driving circuit comprises: a semiconductor layer comprising the first and second active patterns; a first conductive layer comprising the first and second gate electrodes, disposed on the semiconductor layer; a second conductive layer disposed on the first conductive layer; a third conductive layer disposed on the second conductive layer; and a first insulating layer, a second insulating layer, and a third insulating layer respectively interposed between the semiconductor layer and the first conductive layer, between the first and second conductive layers, and between the second and third conductive layers. 5. The OLED display of claim 4 , wherein the first driving circuit comprises a first driving TFT and a first capacitor, and wherein the second driving circuit comprises a second driving TFT and a second capacitor. 6. The OLED display of claim 5 , wherein the first TFT and the second TFT are configured to respectively diode-connect the first driving TFT and the second driving TFT. 7. The OLED display of claim 5 , wherein the first driving TFT comprises i) the first active pattern included in the semiconductor layer of the first driving circuit, ii) the first gate electrode included in the first conductive layer of the first driving circuit, and iii) a first upper electrode overlapping the first gate electrode in the depth dimension of the OLED display, included in the second conductive layer, and disposed on the first gate electrode, and wherein the second driving TFT comprises i) the second driving pattern included in the semiconductor layer of the second driving circuit, ii) the second gate electrode included in the first conductive layer of the second driving circuit, and iii) a second upper electrode overlapping the second gate electrode included in the second conductive layer in the depth dimension of the OLED display, and disposed on the second gate electrode. 8. The OLED display of claim 7 , wherein the light-shielding member and the second upper electrode are disposed on the same layer, and wherein the light-shielding member is spaced apart from the second upper electrode. 9. The OLED display of claim 7 , wherein the light-shielding member extends from a portion of the second upper electrode. 10. The OLED display of claim 7 , wherein the second active pattern comprises a second driving source region and a second driving drain region, wherein the second driving TFT comprises a second driving source electrode electrically connected to the second driving source region and a second driving drain electrode electrically connected to the second driving drain region, and wherein the light-shielding member, the second driving source electrode, and the second driving drain electrode are disposed on the same layer. 11. The OLED display of claim 7 , wherein the third conductive layer comprises a connector that connects the second gate electrode and the second drain region, and wherein the light-shielding member is disposed on a portion of the connector. 12. The OLED display of claim 4 , wherein the third conductive layer comprises a plurality of data lines configured to respectively transfer a plurality of data signals to the first and second driving circuits. 13. The OLED display of claim 12 , wherein the light-shielding member and the data lines are disposed on the same layer, and wherein the light-shielding member is spaced apart from the data lines. 14. The OLED display of claim 1 , wherein the substrate further comprises a third sub-pixel region adjacent to the second sub-pixel region, and wherein the first to third sub-pixel regions respectively correspond to a red sub-pixel region, a green sub-pixel region, and a blue sub-pixel region. 15. The OLED display of claim 1 , wherein the substrate further comprises: a third sub-pixel region adjacent to the second sub-pixel region; a third driving circuit disposed in the third sub-pixel region on the substrate; and a third pixel electrode electrically connected to the third driving circuit, wherein the second pixel electrode is disposed in a first row, wherein the first and third pixel electrodes are disposed in a second row adjacent to the first row, wherein the first and second pixel electrodes are alternately disposed, and wherein the second and third pixel electrodes are alternately disposed. 16. The OLED display of claim 1 , wherein each of the first source region, the first drain region, the second source region, and the second drain region is formed of Si. 17. The OLED display of claim 1 , further comprising: a first organic emission layer interposed between the first pixel electrode and the common electrode; a second organic emission layer interposed between the second pixel electrode and the common electrode; a first common layer interposed between the first and second pixel electrodes, and between the first and second organic emission layers; and a second common layer interposed between the first organic emission layer and the second organic emission layer, and the common electrode, wherein the first common layer comprises at least one of a hole injection layer and a hole transport layer, and wherein the second common layer comprises at least one of an electron transport layer and an electron injection layer. 18. The OLED display of claim 1 , wherein the light-shielding member comprises a metallic layer. 19. The OLED display of claim 1 , wherein the light-shielding member is formed of at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr. 20. The OLED display of claim 17 , wherein the second organic emission layer is configured to e

Assignees

Inventors

Classifications

  • Layout of electrodes and connections · CPC title

  • The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

  • Electricity · mapped topic

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What does patent US9748321B2 cover?
An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate that includes a first sub-pixel region and a second sub-pixel region adjacent to the first sub-pixel region, and a first driving circuit and a second driving circuit respectively disposed in the first sub-pixel region and the second sub-pixel region. The first and second driving circuits includ…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/3262. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 29 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).