Display device

Patent metadata

Field	Value
Publication number	US-10868096-B2
Application number	US-201916287983-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Feb 28, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A display device includes: a substrate; an inorganic insulating layer arranged in a display region, the inorganic insulating layer having a lower valley as an opening or a groove arranged in a region between a first pixel circuit and a second pixel circuit adjacent to each other; a first organic planarization layer arranged over entire regions of the first pixel circuit and the second pixel circuit, the first organic planarization layer filling the lower valley; and a connection wire arranged on the first organic planarization layer, the connection wire connecting the first pixel circuit to the second pixel circuit.

First claim

What is claimed is:

1. A display device comprising:
a substrate comprising a display area and a peripheral area outside the display area, the display area comprising a plurality of pixel circuits and a plurality of display elements respectively connected to the plurality of pixel circuits to display an image;
an inorganic insulating layer arranged in the display area, the inorganic insulating layer having a lower valley as an opening or a groove in a region and arranged between a first pixel circuit and a second pixel circuit that are adjacent to each other;
a first organic planarization layer arranged over entire regions of the first pixel circuit and the second pixel circuit, the first organic planarization layer filling the lower valley; and
a connection wire arranged on the first organic planarization layer, the connection wire connecting the first pixel circuit to the second pixel circuit,
wherein the connection wire is connected to a first conductive layer in the first pixel circuit through a first contact hole passing through the first organic planarization layer and is connected to a second conductive layer in the second pixel circuit through a second contact hole passing through the first organic planarization layer, and
wherein the lower valley surrounds at least one pixel circuit or some pixel circuits from among the plurality of pixel circuits.

2. The display device of claim 1 , wherein the first conductive layer and the second conductive layer are spaced apart from each other by the lower valley, and the first conductive layer and the second conductive layer are arranged on an upper surface of the inorganic insulating layer.

3. The display device of claim 1 , wherein the inorganic insulating layer comprises a first gate insulating layer and a second gate insulating layer arranged on the first gate insulating layer,
wherein the first conductive layer and the second conductive layer are arranged on the first gate insulating layer and are spaced apart from each other by the lower valley, the second gate insulating layer covers the first conductive layer and the second conductive layer, and the first contact hole and the second contact hole pass through the second gate insulating layer.

4. The display device of claim 1 , further comprising an interlayer insulating layer arranged on the connection wire, the interlayer insulating layer having an upper valley as an opening or a groove arranged in a region between the first pixel circuit and the second pixel circuit.

5. The display device of claim 4 , further comprising a second organic planarization layer arranged over the entire regions of the first pixel circuit and the second pixel circuit, the second organic planarization layer filling the upper valley.

6. The display device of claim 1 , wherein the plurality of pixel circuits comprise a third pixel circuit adjacent to the second pixel circuit, the display device further comprising:
an additional connection wire arranged on a same layer as the connection wire, the additional connection wire connecting the second pixel circuit to the third pixel circuit; and
an interlayer insulating layer arranged on the additional connection wire, the interlayer insulating layer having an upper valley in a region between the second pixel circuit and the third pixel circuit.

7. The display device of claim 6 , wherein the additional connection wire is formed integrally with the connection wire.

8. The display device of claim 1 , wherein each of the plurality of pixel circuits comprises a driving thin film transistor and a storage capacitor,
wherein the driving thin film transistor overlaps the storage capacitor.

9. The display device of claim 1 , further comprising:
a bending organic material layer arranged in a bending area bent around a bending axis extending in a first direction in the peripheral region; and
a fan-out wire extending in a second direction crossing the first direction and arranged on the bending organic material layer.

10. A display device comprising a first pixel circuit, a second pixel circuit, and a third pixel circuit, sequentially arranged in a first direction, in a display area for displaying an image, the display device comprising:
an inorganic insulating layer having a first lower valley as an opening or a groove and arranged in a first region between the first pixel circuit and the second pixel circuit;
a first organic planarization layer arranged over entire regions of the first pixel circuit, the second pixel circuit, and the third pixel circuit, the first organic planarization layer filling the first lower valley;
a first connection wire arranged on the first organic planarization layer, the first connection wire overlapping the first region and connecting the first pixel circuit and the second pixel circuit;
a second connection wire arranged on the first organic planarization layer, the second connection wire connecting the second pixel circuit and the third pixel circuit;
an interlayer insulating layer arranged on the first connection wire and the second connection wire, the interlayer insulating layer having a second upper valley as an opening or a groove and arranged in a second region between the second pixel circuit and the third pixel circuit; and
a second organic planarization layer arranged over the entire regions of the first pixel circuit, the second pixel circuit, and the third pixel circuit, the second organic planarization layer filling the second upper valley.

11. The display device of claim 10 , wherein the interlayer insulating layer further has a first upper valley as an opening or a groove that is arranged in the first region.

12. The display device of claim 10 , wherein the inorganic insulating layer further has a second lower valley as an opening or a groove that is arranged in the second region.

13. The display device of claim 10 , further comprising a vertical connection wire arranged on the interlayer insulating layer and extending in a second direction crossing the first direction.

14. The display device of claim 13 , wherein the vertical connection wire comprises a driving voltage line and a data line.

15. The display device of claim 10 , wherein the inorganic insulating layer comprises a first gate insulating layer and a second gate insulating layer arranged on the first gate insulating layer, the display device further comprising:
a first conductive layer arranged on the first gate insulating layer in the first pixel circuit; and
a second conductive layer arranged on the first gate insulating layer in the second pixel circuit,
wherein the first conductive layer and the second conductive layer are spaced apart from each other by the first lower valley, and the first connection wire is connected to the first conductive layer and the second conductive layer respectively through a first contact hole and a second contact hole passing through the first organic planarization layer and the second gate insulating layer.

16. The display device of claim 10 , wherein at least one of the first lower valley and the second upper valley surrounds at least some of the first to third pixel circuits.

17. The display device of claim 10 , wherein each of the first pixel circuit and the second pixel circuit comprises a driving thin film transistor and a storage capacitor that overlap each other,
wherein an upper electrode of the storage capacitor of the first pixel circuit and an upper electrode of the storage capacitor of the second pixel circuit are connected by a mesh connection line that is one of the first connection wire.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Juchan
• Kim Sunho
• Lee Sunhee

Classifications

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/80524

  Transparent cathodes, e.g. comprising thin metal layers · CPC title

• H10K59/80518

  Reflective anodes, e.g. ITO combined with thick metallic layers · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title