Semiconductor device manufacturing method

Patent metadata

Field	Value
Publication number	US-12557370-B2
Application number	US-202218053157-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Nov 9, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor device, the method comprising:
providing a first layer comprising a first surface; forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer, wherein the second layer comprises a second surface that meets the first surface, wherein the second layer comprises a first sub-layer and a second sub-layer spaced apart from each other, and wherein the portion of the first surface not covered by the second layer is between the first sub-layer and the second sub-layer; forming an inhibitor layer on the first surface and the second surface; selectively removing the inhibitor layer from the second surface to expose the second surface; forming an interest layer on the second surface; and removing the inhibitor layer from the first surface by performing an acid treatment process, wherein the inhibitor layer on the first surface reacts with acid or hydrogen ion and is dissociated, wherein physical properties of the first layer are different from physical properties of the second layer.

2 . The method for manufacturing the semiconductor device of claim 1 , wherein the selectively removing the inhibitor layer from the second surface comprises performing a heat treatment process, and
the inhibitor layer on the first surface is not removed by the heat treatment process.

3 . The method for manufacturing the semiconductor device of claim 2 , wherein the heat treatment process is performed at 150° C. or more and 250° C. or less.

4 . The method for manufacturing the semiconductor device of claim 1 , wherein the inhibitor layer comprises at least one of hexamethyldisilazane (HMDS), trimethylsilyldiethylamine, bis(N,N-dimethylamino)dimethylsilane, trimethylsilyldimethylamine, bis(trimethylsilyl) hydrazine, and trimethylchlorosilane.

5 . The method for manufacturing the semiconductor device of claim 1 , wherein a width of the inhibitor layer is 10 Å or less.

6 . The method for manufacturing the semiconductor device of claim 1 , wherein the first layer comprises at least one of titanium nitride, an organic polymer, and a combination thereof.

7 . A method for manufacturing a semiconductor device, the method comprising:
forming a gap fill insulating layer on a titanium nitride layer; etching the gap fill insulating layer to form a first gap fill insulating pattern and a second gap fill insulating pattern, the first gap fill insulating pattern comprising a first surface facing the second gap fill insulating pattern, and the second gap fill insulating pattern comprising a second surface facing the first surface, wherein the first gap fill insulating pattern and the second gap fill insulating pattern expose an upper surface of the titanium nitride layer; forming a first inhibitor layer on the upper surface of the titanium nitride layer; forming a second inhibitor layer on the first surface and the second surface; selectively removing the second inhibitor layer using a heat treatment process to expose the first surface and the second surface; and depositing an interest layer on the first surface and the second surface, wherein the interest layer exposes the first inhibitor layer.

8 . The method for manufacturing the semiconductor device of claim 7 , wherein the first inhibitor layer is not removed by the heat treatment process.

9 . The method for manufacturing the semiconductor device of claim 7 , wherein the heat treatment process is performed at 150° C. or more and 250° C. or less.

10 . The method for manufacturing the semiconductor device of claim 7 , further comprising:
performing an acid treatment process to remove the first inhibitor layer after the depositing the interest layer.

11 . The method for manufacturing the semiconductor device of claim 7 , wherein the first inhibitor layer and the second inhibitor layer comprise at least one of hexamethyldisilazane (HMDS), trimethylsilyldiethylamine, bis(N,N-dimethylamino)dimethylsilane, trimethylsilyldimethylamine, bis(trimethylsilyl) hydrazine, and trimethylchlorosilane.

12 . The method for manufacturing the semiconductor device of claim 7 , wherein the first and second inhibitor layers are formed at 80° C. or more and 240° C. or less.

13 . The method for manufacturing the semiconductor device of claim 7 , wherein a width of the first inhibitor layer is 10 Å or less.

14 . A method for manufacturing a semiconductor device, the method comprising:
forming a first sheet pattern on a first region of a substrate; forming a second sheet pattern on a second region of the substrate; forming a work function metal layer on the substrate, wherein the work function metal layer extends around the first sheet pattern and the second sheet pattern; forming a sacrificial layer on the first and second sheet patterns; forming a trench that penetrates the sacrificial layer between the first sheet pattern and the second sheet pattern, wherein the trench exposes a portion of the work function metal layer; forming an inhibitor layer on a bottom surface and a side surface of the trench; performing a heat treatment process to selectively remove the inhibitor layer from the side surface of the trench; and selectively forming an interest layer on the side surface of the trench, wherein the work function metal layer comprises titanium nitride.

15 . The method for manufacturing the semiconductor device of claim 14 , further comprising:
performing a wet etching process to selectively remove a portion of the work function metal layer that is overlapped by the trench after the selectively forming the interest layer.

16 . The method for manufacturing the semiconductor device of claim 14 , further comprising:
removing the work function metal layer from the first region.

17 . The method for manufacturing the semiconductor device of claim 16 , wherein an NMOS transistor is formed on the first region, and
a PMOS transistor is formed on the second region.

18 . The method for manufacturing the semiconductor device of claim 14 , wherein the heat treatment process is performed at 150° C. or more and 250° C. or less.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Eun Hyea
• Han Hoon
• Hwang Byung Keun
• Mun Jeong Ho
• Song Hyun-Ji
• Cho Youn Joung

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title