Semiconductor structure with fully wrapped-around backside contact

Patent metadata

Field	Value
Publication number	US-12557356-B2
Application number	US-202217967016-A
Country	US
Kind code	B2
Filing date	Oct 17, 2022
Priority date	Oct 17, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a backside contact; and a source/drain region fully disposed within the backside contact; wherein a first portion of the backside contact is disposed in a shallow trench isolation region.

2 . The semiconductor structure according to claim 1 , wherein the first portion of the backside contact has a width greater than a width of the source/drain region.

3 . The semiconductor structure according to claim 1 , wherein a second portion of the backside contact is disposed in an interlayer dielectric layer.

4 . The semiconductor structure according to claim 3 , wherein the source/drain region is disposed above the interlayer dielectric layer.

5 . The semiconductor structure according to claim 3 , further comprising:
a backside interconnect structure disposed on the backside contact and the interlayer dielectric layer.

6 . The semiconductor structure according to claim 1 , further comprising:
a gate structure disposed adjacent the source/drain region.

7 . The semiconductor structure according to claim 6 , further comprising:
a dielectric layer disposed on the gate structure, the dielectric layer separating the gate structure from the backside contact.

8 . The semiconductor structure according to claim 7 , wherein the gate structure is part of a stack of nanosheet channel layers.

9 . The semiconductor structure according to claim 6 , further comprising a frontside interconnect structure disposed over the gate structure.

10 . A semiconductor structure, comprising:
a backside contact; a first source/drain region fully disposed within the backside contact; a frontside contact; and a second source/drain region partially disposed in the frontside contact; wherein a first portion of the backside contact is disposed in a shallow trench isolation region.

11 . The semiconductor structure according to claim 10 , wherein the first portion of the backside contact has a width greater than a width of the first source/drain region.

12 . The semiconductor structure according to claim 10 , wherein a second portion of the backside contact is disposed in an interlayer dielectric layer.

13 . The semiconductor structure according to claim 12 , wherein the first source/drain region and the second source/drain region are disposed above the interlayer dielectric layer.

14 . The semiconductor structure according to claim 10 , further comprising a gate structure.

15 . The semiconductor structure according to claim 14 , further comprising:
a dielectric layer disposed on the gate structure, the dielectric layer separating the gate structure from the backside contact.

16 . The semiconductor structure according to claim 15 , wherein the gate structure is part of a stack of nanosheet channel layers.

17 . The semiconductor structure according to claim 12 , further comprising:
a backside interconnect structure disposed on the backside contact and the interlayer dielectric layer.

18 . An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises: a backside contact; a first source/drain region fully disposed within the backside contact; a frontside contact; and a second source/drain region partially disposed in the frontside contact; wherein a first portion of the backside contact is disposed in a shallow trench isolation region.

19 . The integrated circuit according to claim 18 , wherein the first portion of the backside contact has a width greater than a width of the first source/drain region.

20 . The integrated circuit according to claim 18 , wherein the at least one of the one or more semiconductor structures further comprises:
a gate structure disposed between the first source/drain region and the second source/drain region; and a dielectric layer disposed on the gate structure, the dielectric layer separating the gate structure from the backside contact.

Assignees

• IBM

Inventors

• Xie Ruilong
• Park Chanro
• Sung Min Gyu
• Cheng Kangguo
• Frougier Julien

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title