Dummy memory hole defect detection

Patent metadata

Field	Value
Publication number	US-12555643-B2
Application number	US-202418635219-A
Country	US
Kind code	B2
Filing date	Apr 15, 2024
Priority date	Apr 15, 2024
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Technology for detection of defects in dummy memory holes in a 3D NAND memory structure. Dummy bit lines connected to dummy memory holes are used to detect defects associated with the dummy memory holes. A system may perform a stress test in which a stress voltage is applied to one or more word lines while another voltage (e.g., 0V) is applied to the dummy bit lines. The system may detect defects associated with the dummy memory holes by sensing the dummy bit lines. The dummy bit lines may be electrically connected with each other which reduces the amount of circuitry for providing a voltage to the dummy bit lines and/or sensing the dummy bit lines.

First claim

What is claimed is:

1 . An apparatus comprising:
a three-dimensional NAND memory structure having a plurality of blocks, each block comprising a plurality of word line layers, a source line, operational NAND strings each having a NAND channel electrically connected to the source line, and dummy NAND strings each having a conductive channel that is insulated from the source line, the word line layers in a particular block connected to the operational NAND strings and the dummy NAND strings, the three-dimensional NAND memory structure having bit lines in electrical contact with the conductive channels of the dummy NAND strings, the dummy NAND strings are not eligible to store data; and one or more control circuits in communication with the three-dimensional NAND memory structure, the one or more control circuits configured to:
sense one or more signals on the bit lines connected to the conductive channels of the dummy NAND strings; and
determine whether there is an electrical short defect associated with the dummy NAND strings based on the one or more signals.

2 . The apparatus of claim 1 , wherein:
the bit lines in electrical contact with the conductive channels of the dummy NAND strings are electrically connected with each other; and the one or more control circuits comprise a sense node configured to sense the one or more signals on the electrically connected bit lines.

3 . The apparatus of claim 2 , wherein the one or more control circuits are further configured to turn on drain select transistors in a selected block in the three-dimensional NAND memory structure while applying a first voltage to one or more of the word line layers in the selected block and while applying a second voltage to the electrically connected bit lines in the selected block, the second voltage being a different magnitude than the first voltage.

4 . The apparatus of claim 3 , wherein the difference in magnitude between the first voltage and the second voltage is a stress voltage that accelerates potential electrical short defects associated with the dummy NAND strings.

5 . The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to turn on drain select transistors in a selected block in the three-dimensional NAND memory structure while applying a test voltage to one or more of the word line layers in the selected block, the test voltage having a magnitude configured to test for leakage current between the conductive channel of any of the dummy NAND strings and any of the one or more of the word line layers to which the test voltage is applied; and the one or more control circuits sense the one or more signals on the bit lines in electrical contact with the conductive channels of the dummy NAND strings in response to applying the test voltage to the one or more of the word line layers to determine whether there is the electrical short defect associated with the dummy NAND strings.

6 . The apparatus of claim 1 , wherein:
the dummy NAND strings reside in a first region of a particular block having first dummy holes that extend vertically through the plurality of word line layers, each first dummy hole having approximately a first diameter in a particular word line layer; each block in the three-dimensional NAND memory structure further comprises a group of second dummy holes in a second region of the particular block that extend vertically through the plurality of word line layers, each second dummy hole having approximately a second diameter in the particular word line layer that is greater than the first diameter, each second dummy hole having a conductive region surrounded by an insulator; and the apparatus comprises bit lines electrically connected to the conductive region of the respective second dummy holes.

7 . The apparatus of claim 6 , wherein the one or more control circuits are further configured to:
apply a voltage to one or more of the word line layers in a selected block in the three-dimensional NAND memory structure; sense a signal on the bit lines electrically connected to the second dummy holes in response to the voltage applied to the one or more of the word line layers in the selected block; and determine whether there is an electrical short defect in the second dummy holes based on the signal on the bit lines electrically connected to the second dummy holes.

8 . The apparatus of claim 7 , wherein the bit lines electrically connected to the second dummy holes are electrically connected to each other.

9 . The apparatus of claim 8 , wherein the one or more control circuits comprise a sense node configured to sense the signal on the electrically connected bit lines connected to the second dummy holes to test for a leakage current indicative of the electrical short defect in the second dummy holes.

10 . A method comprising:
applying a voltage to one or more word lines of a plurality of word lines in a block in a three dimensional NAND memory structure, the plurality of word lines connected to dummy memory holes in the block, each dummy memory hole comprises a conductive memory cell film that extends through the word lines in the block, the conductive memory cell film of each dummy memory hole electrically connected to electrically connected dummy bit lines, the dummy memory holes are not eligible to store data; sensing a signal on the electrically connected dummy bit lines; and determining whether there is a defect associated with the dummy memory holes based on the sensing of the electrically connected dummy bit lines, wherein the defect includes an electrical short between the conductive memory cell film of any of the dummy memory holes and any of the one or more word lines of the plurality of word lines.

11 . The method of claim 10 , further comprising applying a stress voltage to at least one word line of the plurality of word lines in the block while applying a voltage lower than the stress voltage to the electrically connected dummy bit lines from a single voltage driver, the stress voltage configured to accelerate a potential electrical short between the conductive memory cell film of any of the dummy memory holes and any of the at least one or more word line of the plurality of word lines.

12 . The method of claim 10 , wherein sensing the signal on the electrically connected dummy bit lines comprises:
applying a sensing voltage to the electrically connected dummy bit lines from a single voltage driver; and sensing the signal on the electrically connected dummy bit lines at a single sense node.

13 . A non-volatile storage system, the storage system comprising:
a three-dimensional NAND memory structure having blocks, each block comprising:
alternating conductive layers and insulating layers;
memory holes that extend vertically through the alternating conductive and insulating layers, each memory hole having memory cell film layers including a channel layer, wherein a first group of the memory holes in a first region in a particular block have their respective channel layer in direct electrical contact with a source line of the particular block, wherein a second group of the memory holes in a second region of the particular block have their respective channel layer electrically isolated from the source line of the particular block, the second group of the memory holes are not eligible to store data; and
a plurality of bit lines that extend over the blocks; and one or more control circuits in communication with the blocks and the bit lines, the one or more control circuits configured to:
apply a first voltage to at least one conductive layer of the conductive layers in a selected b

Assignees

• Sandisk Technologies Inc

Inventors

• IKAWA Yusuke
• Hu Xiaolong
• Samura Kei

Classifications

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title