Systems and methods for compensating for erase speed variations due to semi-circle SGD

Patent metadata

Field	Value
Publication number	US-11545226-B1
Application number	US-202117355684-A
Country	US
Kind code	B1
Filing date	Jun 23, 2021
Priority date	Jun 23, 2021
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.

First claim

What is claimed is:

1. A method for programming a memory device, the method comprising:
programming one or more select gates of a first row of memory holes to a first threshold voltage, wherein the one or more select gates of the first row of memory holes defines define full circle drain side select gate (FC-SGD);
causing, based on the first threshold voltage, the one or more select gates of the first row of memory holes to include a first erase speed;
programming one or more select gates of a second row of memory holes to a second threshold voltage different from the first threshold voltage, wherein the one or more select gates of the second row of memory holes defines semi-circle drain side select gate (SC-SGD); and
causing, based on the second threshold voltage, the one or more select gates of the second row of memory holes to include a second erase speed that is at least within a threshold erase speed of the first erase speed.

2. The method according to claim 1 , wherein the second erase speed matches the first erase speed.

3. The method according to claim 1 , wherein:
programming the one or more select gates of the first row of memory holes comprises applying a first programming voltage, and
programming the one or more select gates of the second row of memory holes comprises applying a second programming voltage that is greater than the first programming voltage.

4. The method according to claim 1 , further comprising, prior to programming the one or more select gates of the first row and the one or more select gates of the second row:
determining whether the one or more select gates of the second row of memory holes defines the SC-SGD; and
programming the one or more select gates of the second row of memory holes based upon a predetermined verify level.

5. The method according to claim 1 , further comprising, prior to programming the one or more select gates of the first row of memory holes and the one or more select gates of the second row memory holes:
providing an erase pulse to one or more select gates of the first row of memory holes and the one or more select gates of the second row of memory holes; and
determining, based on the erase pulse, a first erase speed of the one or more select gates of the first row of memory holes and a second erase speed of the one or more select gates of the second row of memory holes.

6. The method according to claim 5 , further comprising, when the first erase speed is faster than the second erase speed, setting the second threshold voltage higher than the first threshold voltage.

7. The method according to claim 1 , wherein:
the one or more select gates of the first row of memory holes are located in a first row of a memory block of the memory device, and
the one or more select gates of the second row of memory holes are located in a second row of the memory block.

8. A memory system, comprising:
a memory device; and
a controller operatively coupled to the memory device, the controller configured to:
program one or more select gates of a first row of memory holes to a first threshold voltage, wherein the first row of memory holes defines define full circle drain side select gate (FC-SGD);
cause, based on the first threshold voltage, the first row of memory holes to include a first erase speed;
program one or more select gates of a second row of memory holes to a second threshold voltage different from the first threshold voltage, wherein the second row of memory holes defines semi-circle drain side select gate (SC-SGD); and
cause, based on the second threshold voltage, the second row of memory holes to include a second erase speed that is at least within a threshold erase speed of the first erase speed.

9. The memory system according to claim 8 , wherein the second erase speed matches the first erase speed.

10. The memory system according to claim 8 , wherein the controller is further configured to:
program the one or more select gates of the first row of memory holes comprises applying a first programming voltage, and
program the one or more select gates of the second row of memory holes comprises applying a second programming voltage that is greater than the first programming voltage.

11. The memory system according to claim 8 , wherein the controller is further configured to, prior to programming the first row and the second row:
determine whether the one or more select gates of the second row of memory holes defines the SC-SGD; and
program the one or more select gates of the second row of memory holes based upon a predetermined verify level.

12. The memory system according to claim 8 , wherein the controller is further configured to, prior to programming the first row and the second row:
provide an erase pulse to one or more select gates of the first row of memory holes and the one or more select gates of the second row of memory holes; and
determine, based on the erase pulse, a first erase speed of the one or more select gates of the first row of memory holes and a second erase speed of the one or more select gates of the second row of memory holes.

13. The memory system according to claim 12 , wherein the controller is further configured to, when the first erase speed is faster than the second erase speed, set the second threshold voltage higher than the first threshold voltage.

14. The memory system according to claim 8 , wherein:
the one or more select gates of the first row of memory holes are located in a first row of a memory block of the memory device, and
the one or more select gates of the second row of memory holes are located in a second row of the memory block.

15. A non-transitory computer readable storage medium configured to store instructions that, when executed by a processor included a controller of a memory system, cause the memory system to carry out steps to:
program one or more select gates of a first row of memory holes to a first threshold voltage, wherein the first row of memory holes defines define full circle drain side select gate (FC-SGD);
cause, based on the first threshold voltage, the first row of memory holes to include a first erase speed;
program one or more select gates of a second row of memory holes to a second threshold voltage different from the first threshold voltage, wherein the second row of memory holes defines semi-circle drain side select gate (SC-SGD); and
cause, based on the second threshold voltage, the second row of memory holes to include a second erase speed that is at least within a threshold erase speed of the first erase speed.

16. The non-transitory computer readable storage medium according to claim 15 , wherein the second erase speed matches the first erase speed.

17. The non-transitory computer readable storage medium according to claim 15 , wherein the instructions further cause the memory system to carry out steps to:
program the one or more select gates of the first row of memory holes comprises applying a first programming voltage, and
program the one or more select gates of the second row of memory holes comprises applying a second programming voltage that is greater than the first programming voltage.

18. The non-transitory computer readable storage medium according to claim 15 , wherein the instructions further cause the memory system to carry out steps to, prior to programming the first row and the second row:
determine whether the one or more select gates of the second row of memory holes defines the SC-SGD; and
program the one or more select gates of the second row of memory holes based upo

Assignees

• Sandisk Technologies Llc

Inventors

• Prakash Abhijith
• Yang Xiang

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title