Vertical-type non-volatile memory devices having dummy channel holes

Patent metadata

Field	Value
Publication number	US-RE49440-E
Application number	US-202117201958-A
Country	US
Kind code	E1
Filing date	Mar 15, 2021
Priority date	Jan 3, 2014
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A vertical-type nonvolatile memory device, comprising:
a substrate; a channel structure extending in a first direction perpendicular to the substrate; a plurality of memory cell stacks respectively comprising a ground selection line, a plurality of word lines, and a string selection line, wherein the ground selection line, the plurality of word lines, and the string selection line are sequentially stacked so as to be separate from each other on a side surface of the channel structure in the first direction; a common source region on a first surface of the substrate between ones of the plurality of memory cell stacks; a recess region, which has a bottom corresponding to a second surface lower than the first surface of the substrate, in the substrate, the recess region comprising a first channel material layer therein; and a dummy channel structure contacting a sidewall of the common source region and overlapping a portion of an upper surface of the first channel material layer in the first direction.

2. The vertical-type nonvolatile memory device of claim 1 , wherein the upper surface of the first channel material layer is higher than an upper surface of the substrate on which the common source region is provided.

3. The vertical-type nonvolatile memory device of claim 1 , wherein the first channel material layer contacts the sidewall of the common source region.

4. The vertical-type nonvolatile memory device of claim 1 , wherein a channel hole recess region, which is lower than the bottom of the recess region, is provided on the substrate.

5. A vertical-type nonvolatile memory device, comprising:
a substrate; a channel structure extending from the substrate in a first direction perpendicular to the substrate; a plurality of memory cell stacks respectively comprising a ground selection line, a plurality of word lines, and a to string selection line, wherein the ground selection line, the plurality of word lines, and the string selection line are sequentially stacked so as to be separate from each other on a side surface of the channel structure in the first direction; a common source region on a first surface of the substrate between ones of the plurality of memory cell stacks; and a recess region, which has a bottom corresponding to a second surface lower than the first surface of the substrate, in the substrate, and further comprising:
a channel hole recess region, which is lower than the bottom of the recess region, on the substrate; or
a channel hole protruding portion, which is higher than the bottom of the recess region and is lower than an upper surface of the substrate, on the substrate.

6. A vertical-type nonvolatile memory device, comprising:
a substrate; a channel structure extending from the substrate in a first direction perpendicular to the substrate; a plurality of word lines sequentially stacked so as to be spaced apart from each other along a side surface of the channel structure in the first direction; a common source region between stacks of the plurality of word lines; and at least one dummy channel structure adjacent a sidewall of the common source region, wherein the at least one dummy channel structure is disposed between the channel structure and the common source region, wherein a distance between the at least one dummy channel structure and the channel structure on a word line closest to the at least one dummy channel structure is larger than a distance between the channel structure and another channel structure on the word line.

7. The vertical-type nonvolatile memory device of claim 6 , wherein the at least one dummy channel structure comprises as a plurality of dummy channel structures that are disposed in a line in a second direction perpendicular to the first direction.

8. The vertical-type nonvolatile memory device of claim 6 , wherein the at least one dummy channel structure comprises a channel layer and a charge storage layer, wherein a surface of the at least one dummy channel structure, which faces the common source region, is covered with a blocking insulating layer.

9. The vertical-type nonvolatile memory device of claim 6 , wherein the at least one dummy channel structure comprises a dummy hole defining an unobstructed space therein.

10. The vertical-type nonvolatile memory device of claim 6 , wherein an inside of the at least one dummy channel structure comprises an insulating material.

11. The vertical-type nonvolatile memory device of claim 10 , further comprising a plurality of word line contacts on the plurality of word lines and connected to the plurality of word lines, respectively, wherein the dummy channel structure is disposed adjacent a periphery of the plurality of word line contacts.

12. The vertical-type nonvolatile memory device of claim 6 , wherein the common source region is on a first surface of the substrate, and the at least one dummy channel structure is on a second surface having a level that is different from that of the first surface of the substrate.

13. A vertical-channel nonvolatile memory device, comprising:
a substrate including channel hole recess regions in a surface thereof; channel structures vertically protruding from the surface of the substrate on ones of the channel hole recess regions; memory cell stacks comprising insulating and conductive layers alternately stacked along sidewalls of the channel structures; and a common source line extending along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region that separates adjacent ones of the memory cell stacks, wherein a distance between the ones of the channel hole recess regions having the channel structures thereon and the other ones of the channel hole recess regions immediately adjacent thereto is greater than a distance between the ones of the channel hole recess regions immediately adjacent one another.

14. The device of claim 13 , further comprising:
non-functional channel contact structures comprising a channel material layer in the other ones of the channel hole recess regions.

15. The device of claim 14 , further comprising:
non-functional dummy channel structures vertically protruding from the substrate surface on the other ones of the channel hole recess regions adjacent sidewalls of the common source line.

16. The device of claim 13 , wherein respective surfaces of the word line recess region and the other ones of the channel hole recess regions are non-coplanar.

17. A vertical-type nonvolatile memory device, comprising:
a substrate; a channel structure extending from the substrate in a first direction perpendicular to the substrate, the channel structure being disposed in a channel hole; a plurality of memory cell stacks respectively comprising a ground selection line, a plurality of word lines, and a string selection line, wherein the ground selection line, the plurality of word lines, and the string selection line are sequentially stacked so as to be separate from each other on a side surface of the channel structure in the first direction; a word line recess region on a first surface of the substrate between ones of the plurality of memory cell stacks, wherein the first surface is lower than an upper surface of the substrate; and a channel hole recess region, which has a bottom corresponding to a second surface lower than the first surface of the substrate, in the substrate, wherein a bottom of the word line recess region is lower than a bottom of the channel hole.

18. The vertical-type nonvolatile memory d

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Hyun

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B41/30 Primary

  characterised by the memory core region · CPC title