Three dimensional NAND device having dummy memory holes and method of making thereof

Patent metadata

Field	Value
Publication number	US-9887207-B2
Application number	US-201414462209-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Aug 18, 2014
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.

First claim

What is claimed is:

1. A monolithic three dimensional NAND string, comprising:
a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, and wherein the plurality of control gate electrodes extend through at least one memory cell region and at least one dummy channel region;
an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;
a memory opening located in the at least one memory cell region and extending substantially perpendicular to the major surface of the substrate, the memory opening filled with a memory opening material comprising:
a semiconductor channel located at least partially in the memory opening, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the substrate, at least one first portion of the semiconductor channel located in a first device level, and at least one second portion of the semiconductor channel located in a second device level; and
at least one memory film located at least partially in the memory opening and adjacent to the semiconductor channel;

one of a source or drain electrode which contacts the semiconductor channel from above or below; and
at least one dummy opening having a circular cross sectional shape when viewed from above located in the at least one dummy channel region, the at least one dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material, wherein the dummy channel material contacts a sidewall of the interlevel insulating layer in the dummy opening;
wherein the dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.

2. The monolithic three dimensional NAND string of claim 1 , further comprising an electrode shunt extending substantially parallel to the major surface of the substrate and connected to the one of the source or drain electrode, the electrode shunt comprising a conductive electrode shunt material, wherein the dummy channel region is located under the electrode shunt.

3. The monolithic three dimensional NAND string of claim 1 , wherein the dummy channel material comprises a material under compressive stress and the plurality of control gate electrodes are under tensile stress.

4. The monolithic three dimensional NAND string of claim 1 , wherein the dummy channel material comprises a single material or a combination of more than one material, and the single dummy channel material or the combination dummy channel material has a higher Young's modulus than the memory opening material.

5. The monolithic three dimensional NAND string of claim 1 , wherein:
the plurality of control gate electrodes comprise an electrically conductive material; and
the dummy channel material comprises an electrically insulating material, or an electrically insulating shell and an electrically conductive or semiconductor core.

6. The monolithic three dimensional NAND string of claim 5 , wherein:
the semiconductor channel material comprises silicon;
the plurality of control gate electrodes comprise tungsten or a tungsten alloy; and
the dummy channel material comprises silicon nitride, or a silicon oxide shell and a tungsten core.

7. The monolithic three dimensional NAND string of claim 1 , wherein the at least one memory film comprises:
a blocking dielectric located in contact with the plurality of control gate electrodes and the interlevel insulating layer;
at least one charge storage region located at least partially in contact with the blocking dielectric; and
a tunnel dielectric located between the at least one charge storage region and the semiconductor channel.

8. The monolithic three dimensional NAND string of claim 7 , further comprising an insulating core fill layer contacting the semiconductor channel.

9. The monolithic three dimensional NAND string of claim 1 ,
wherein the semiconductor channel has a pillar shape and extends substantially perpendicular to the major surface of the substrate; and
further comprising one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above, and another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

10. The monolithic three dimensional NAND string of claim 1 ,
wherein the semiconductor channel has U-shaped pipe shape,
wherein two wing portions of the U-shaped pipe shape semiconductor channel extend substantially perpendicular to the major surface of the substrate and a connecting portion of the U-shaped pipe shape semiconductor channel which connects the two wing portions extends substantially parallel to the major surface of the substrate; and
wherein the one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and
further comprising another one of a source or drain electrode which contacts the second wing portion of the semiconductor channel from above.

11. The monolithic three dimensional NAND string of claim 2 , wherein:
the semiconductor channel has J-shaped pipe shape;
a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate; and
the one of a source or drain electrode comprises a drain electrode contacts the first wing portion of the semiconductor channel from above; and
further comprising a source electrode which contacts the connecting portion of the semiconductor channel from above.

12. The monolithic three dimensional NAND string of claim 11 , wherein:
the source electrode comprises a rail shaped electrode which electrically contacts the electrode shunt;
the source electrode is located in a dielectric insulated trench;
the source electrode extends substantially parallel to the plurality of control gate electrodes and substantially perpendicular to the electrode shunt;
the drain electrode is electrically connected to a bit line which is located above the semiconductor channel;
the bit line extends substantially perpendicular to the plurality of control gate electrodes and to the source electrode, and substantially parallel to the electrode shunt.

13. A method of making a monolithic three dimensional NAND string, comprising:
forming a stack of alternating first layers and second layers, wherein the stack of alternating first layers and second layers extend substantially parallel to a major surface of a substrate;
etching the stack to form at least one memory opening and at least one dummy opening having a circular cross sectional shape when viewed from above, the at least one memory opening and the dummy opening extending substantially perpendicular to the major surface of the substrate;
forming a memory opening material comprising a semiconductor channel and a memory film in the at least one memory opening;
forming a dummy channel material which is different from the memory opening ma

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Makala Raghuveer S
• Alsmeier Johann
• Lee Yao Sheng
• Xu Tiger

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H01L29/7845

  Electricity · mapped topic