Store-to-load forwarding for processor pipelines

Patent metadata

Field	Value
Publication number	US-12554650-B2
Application number	US-202418747414-A
Country	US
Kind code	B2
Filing date	Jun 18, 2024
Priority date	Dec 21, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Systems and methods are disclosed for store-to-load forwarding for processor pipelines. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor pipeline; a store queue that has entries associated with respective store instructions that are being executed, wherein an entry of the store queue includes a tag that is determined based on a virtual address of a target of the associated store instruction; and store-to-load forwarding circuitry that is configured to: compare a first virtual address of a target of a first load instruction being executed by the load unit to respective tags of one or more entries in the store queue; select an entry of the store queue based on a match between the first virtual address and the tag of the selected entry; and forward data of the selected entry in the store queue to be returned by the first load instruction.

First claim

What is claimed is:

1 . A method comprising:
determining a match between a first virtual address of a first load instruction being executed by a load unit and a tag of an entry in a store queue, wherein the entry includes the tag that is determined by a function that combines a plurality of bits of a virtual address of a store instruction to generate a new value, wherein the tag is separate from the virtual address; selecting the entry based on the match; and forwarding data of the entry in the store queue to be returned by the first load instruction.

2 . The method of claim 1 , wherein the first virtual address is compared to tags of entries in the store queue before a first physical address is determined based on the first virtual address using a translation lookaside buffer.

3 . The method of claim 2 , further comprising:
checking that one or more forwarding conditions are satisfied by comparing the first physical address to a physical address in a miss status holding register with a tag that matches the tag of the entry.

4 . The method of claim 1 , wherein the function is a hash function such that the tag of the entry is a hash of the virtual address of the store instruction.

5 . The method of claim 1 , wherein selecting the entry comprises:
prioritizing matching entries of the store queue with tags that match the first virtual address based on program order of respective instructions associated with the matching entries to select the selected entry as corresponding to a most recent instruction before the first load instruction.

6 . An integrated circuit comprising:
a processor pipeline including a load unit for executing load instructions and a store unit for executing store instructions; a store queue that has entries associated with respective store instructions that are being executed by the store unit, wherein an entry of the entries includes a tag that is determined by a function that combines a plurality of bits of a virtual address of a store instruction to generate a new value, wherein the tag is separate from the virtual address; and store-to-load forwarding circuitry that is configured to:
determine a match between a first virtual address of a first load instruction being executed by the load unit and the tag of the entry;
select the entry of the store queue based on the match; and
forward, based on the entry being selected, data of the entry in the store queue to be returned by the first load instruction.

7 . The integrated circuit of claim 6 , further comprising:
a translation lookaside buffer configured to translate virtual addresses to physical addresses, wherein the first virtual address is compared to tags of the entries before a first physical address is determined based on the first virtual address using the translation lookaside buffer.

8 . The integrated circuit of claim 7 , further comprising:
a set of miss status holding registers, wherein a miss status holding register in the set of miss status holding registers includes the tag in an entry of the store queue and a physical address of the associated store instruction.

9 . The integrated circuit of claim 8 , wherein the store-to-load forwarding circuitry is configured to:
check that one or more forwarding conditions are satisfied by comparing the first physical address to a physical address in the miss status holding register with a tag that matches the tag of the entry.

10 . The integrated circuit of claim 6 , wherein the function is a hash function such that the tag of the entry is a hash of the virtual address of the store instruction.

11 . The integrated circuit of claim 6 , wherein the store-to-load forwarding circuitry is further configured to:
prioritize matching entries of the store queue with tags that match the first virtual address based on program order of respective instructions associated with the matching entries to select the entry as corresponding to a most recent instruction before the first load instruction.

12 . The integrated circuit of claim 6 , wherein the load unit and the store unit are integrated in a load/store unit of the processor pipeline.

13 . A system comprising:
a processor pipeline including a load unit for executing load instructions and a store unit for executing store instructions; a store queue that has entries associated with respective store instructions that are being executed by the store unit, wherein an entry of the entries includes a tag that is determined by a function that combines a plurality of bits of a virtual address of a store instruction to generate a new value, wherein the tag is separate from the virtual address; a set of miss status holding registers, wherein a miss status holding register in the set of miss status holding registers includes the tag and a physical address of the store instruction; and store-to-load forwarding circuitry that is configured to:
determine a match between a first virtual address of a first load instruction being executed by the load unit and the tag of the entry;
select the entry of the store queue based on the match; and
forward, based on the entry being selected, data of the entry in the store queue to be returned by the first load instruction.

14 . The system of claim 13 , further comprising:
a translation lookaside buffer configured to translate virtual addresses to physical addresses, wherein the first virtual address is compared to tags of the entries in the store queue before a first physical address is determined based on the first virtual address using the translation lookaside buffer.

15 . The system of claim 14 , wherein the store-to-load forwarding circuitry is further configured to:
check that one or more forwarding conditions are satisfied by comparing the first physical address to a physical address in a miss status holding register in the set of miss status holding registers with a tag that matches the tag of the selected entry.

16 . The system of claim 13 , wherein the store-to-load forwarding circuitry is further configured to:
prioritize matching entries of the store queue with tags that match the first virtual address based on program order of respective instructions associated with the matching entries to select the entry as corresponding to a most recent instruction before the first load instruction.

Assignees

• Sifive Inc

Inventors

• Ingalls John

Classifications

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title