Techniques for performing store-to-load forwarding

Patent metadata

Field	Value
Publication number	US-11113056-B2
Application number	US-201916698808-A
Country	US
Kind code	B2
Filing date	Nov 27, 2019
Priority date	Nov 27, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A technique for performing store-to-load forwarding is provided. The technique includes determining a virtual address for data to be loaded for the load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions, determining a physical address for the load instruction, and validating the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

First claim

What is claimed is:

1. A method for performing store-to-load forwarding for a load instruction, the method comprising:
determining a virtual address for data to be loaded for the load instruction;
identifying a matching store instruction from one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions;
placing the load instruction into a load waiting buffer in response to detecting that the matching store instruction has not yet received an address translation when initiating validation of the load instruction;
and
validating the load instruction based on a comparison between a physical address of the load instruction and a physical address of the matching store instruction.

2. The method of claim 1 , wherein determining the virtual address for the data to be loaded for the load instruction comprises:
performing one or more calculations on address values as specified by the load instruction to obtain the virtual address.

3. The method of claim 1 , wherein the one or more store instruction memories includes at least one of:
a store queue configured to store store instructions that are executing and have not yet retired; and
a store commit queue configured to store store instructions that have retired and whose store data has not been committed to a memory system.

4. The method of claim 1 , further comprising determining the physical address for the load instruction by performing an address translation to translate the virtual address for the data to be loaded for the load instruction to the physical address for the load instruction.

5. The method of claim 1 , further comprising:
in response to receiving a physical address for the store instruction, applying the physical address for the store instruction to the load waiting buffer to determine whether the physical address of the store instruction matches the physical address of the load instruction.

6. The method of claim 1 , wherein validating the load instruction comprises:
at time of initiation of the validating, detecting that the matching store instruction has received an address translation; and
comparing the physical address of the load instruction to the physical address of the matching store instruction.

7. The method of claim 1 , wherein the virtual-address-based comparison value for the load instruction based on the virtual address for the data for the load instruction comprises one of:
a hash of a portion of the virtual address for the load instruction;
a hash of the full virtual address for the load instruction;
a portion of the virtual address for the load instruction; and
the full virtual address for the load instruction.

8. The method of claim 1 , further comprising:
in response to successfully validating the load instruction, allowing the load instruction to complete execution without flushing the load instruction; or
in response to unsuccessfully validating the load instruction, flushing the load instruction and replaying the load instruction.

9. A load/store subsystem for performing store-to-load forwarding for a load instruction, the load/store subsystem comprising:
one or more store instruction memories; and
a load/store unit configured to:
determine a virtual address for data to be loaded for the load instruction;
identify a matching store instruction from the one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions;
place the load instruction into a load waiting buffer in response to detecting that the matching store instruction has not yet received an address translation when initiating validation of the load instruction;
and
validate the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction.

10. The load/store subsystem of claim 9 , wherein determining the virtual address for the data to be loaded for the load instruction comprises:
performing one or more calculations on address values as specified by the load instruction to obtain the virtual address.

11. The load/store subsystem of claim 9 , wherein the one or more store instruction memories includes at least one of:
a store queue configured to store store instructions that are executing and have not yet retired; and
a store commit queue configured to store store instructions that have retired and whose store data has not been committed to a memory system.

12. The load/store subsystem of claim 9 , wherein the load/store unit is further configured to determine the physical address for the load instruction by performing an address translation to translate the virtual address for the data to be loaded for the load instruction to the physical address for the load instruction.

13. The load/store subsystem of claim 9 , wherein the load/store unit is further configured to:
in response to receiving a physical address for the store instruction, apply the physical address for the store instruction to the load waiting buffer to determine whether the physical address of the store instruction matches the physical address of the load instruction.

14. The load/store subsystem of claim 9 , wherein validating the load instruction comprises:
at time of initiation of the validating, detecting that the matching store instruction has received an address translation; and
comparing the physical address of the load instruction to the physical address of the matching store instruction.

15. The load/store subsystem of claim 9 , wherein the virtual-address-based comparison value for the load instruction based on the virtual address for the data for the load instruction comprises one of:
a hash of a portion of the virtual address for the load instruction;
a hash of the full virtual address for the load instruction;
a portion of the virtual address for the load instruction; and
the full virtual address for the load instruction.

16. The load/store subsystem of claim 9 , wherein the load/store unit is further configured to:
in response to successfully validating the load instruction, allowing the load instruction to complete execution without flushing the load instruction; or

in response to unsuccessfully validating the load instruction, flushing the load instruction and replaying the load instruction.

17. A processing unit for performing store-to-load forwarding for a load instruction, the processing unit comprising:
one or more store instruction memories;
a load/store unit configured to:
determine a virtual address for data to be loaded for the load instruction;
identify a matching store instruction from the one or more store instruction memories by comparing a virtual-address-based comparison value for the load instruction to one or more virtual-address-based comparison values of one or more store instructions;
place the load instruction into a load waiting buffer in response to detecting that the matching store instruction has not yet received an address translation when initiating validation of the load instruction;
and
validate the load instruction based on a comparison between the physical address of the load instruction and a physical address of the matching store instruction; and
a data translation lookaside buffer configured to translate the virtual address for the load instruction to the physical address for the

Assignees

• Advanced Micro Devices Inc

Inventors

• King John M
• Sobel Matthew T

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title