Conditioning store-to-load forwarding (STLF) on past observations of STLF propriety

Patent metadata

Field	Value
Publication number	US-11989286-B2
Application number	US-202217575220-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	May 7, 2021
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

A method and system for mitigating against side channel attacks (SCA) that exploit speculative store-to-load forwarding is described. The method comprises conditioning store-to-load forwarding on the memory dependence predictor (MDP) being trained for that load instruction. Training involves identifying situations in which store-to-load forwarding could have been performed, but wasn't, and obversely, identifying situations in which store-to-load forwarding was performed but resulted in an error.

First claim

The invention claimed is:

1. A method of mitigating side channel attacks (SCAB) that exploit speculative store-to-load forwarding in a processor, the method comprising:
executing one or more store instructions, each of which has a store data address;
beginning execution of a load instruction, which has a load data address, before the one or more store instructions commit;
checking whether a record of the load instruction exists that predicts whether store data is available from an uncommitted store instruction for forwarding to the load instruction;
performing a partial or full comparison between the load instruction's virtual or physical data address and the virtual or physical data addresses of the one or more store instructions;
when (a) said record exists, (b) the comparison finds a data address match between the load instruction and one of the one or more store instructions, and (c) said one store instruction is a most recent store instruction, older than the load instruction, that has a matching data address, forwarding the store data of said one store instruction to the load instruction;

when no said record exists, refraining from forwarding and sourcing the load data from a cache, even when the comparison finds said data address match.

2. The method of claim 1 , further comprising:
when said forwarding is abstained from but the data from the store instruction was valid and available to forward to the load instruction, creating or adding to a record thereof.

3. The method of claim 1 , wherein said form of comparison is a comparison of partial load data address with one or more partial store data addresses.

4. The method of claim 1 , wherein said form of comparison is a comparison of a part or all of a load data address with a part or all of one or more of the store data addresses, wherein the load and store data addresses are virtual.

5. The method of claim 3 , further comprising performing a second comparison that confirms whether a full physical data address of the load data matches the full physical data addresses of one or more of the store instructions.

6. The method of claim 1 , wherein the record is stored in a memory dependence predictor (MDP).

7. The method of claim 1 , wherein the record is a cumulative indicator of the propriety of store-to-load forwarding of a plurality of past instances in which the load instruction was executed.

8. The method of claim 7 , wherein the cumulative indicator is a function of instances in which forwarding that did not occur would have been valid, instances in which forwarding that did not occur would not have been valid, instances in which forwarding that did occur was verified to be valid, and instances in which forwarding that did occur resulted in an abort.

9. The method of claim 7 , wherein separate records of the propriety of store-to-load forwarding for the load instruction are kept for different execution environments in which the load instruction was executed.

10. The method of claim 7 , wherein the record includes a translation context (TC) for the load instruction, the method further comprising:
comparing the recorded TC with the load instruction's TC, and when they do not match, refraining from forwarding and sourcing the load data from the cache;
wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.

11. An out-of-order and speculative execution processor comprising:
an out-of-order, speculative-executing execution pipeline;
a memory dependence predictor (MDP) that predicts whether load instructions could validly forward store data from earlier store instructions;
wherein the predictions are based upon records of one or more previous instances of the load instructions executing;
MDP training logic that, after a load instruction and store instruction progress far enough through an execution pipeline that they can no longer be aborted by an earlier instruction or cause an abort themselves, determines whether a committed load instruction received, or could have received, valid store data from the store instruction, and causes that determination to be incorporated into a record of the MDP for that load instruction; and
store-to-load-forwarding logic that conditions forwarding of store data from a store instruction to a load instruction on the MDP having a record and a prediction that said forwarding would be valid;
wherein when said conditions are not met, refraining from store-to-load forwarding and supplying store data from the cache, even when the load and store data addresses match or are, on the basis of a partial or full virtual or physical address comparison, predicted to match.

12. The apparatus of claim 11 , wherein the MDP training logic makes said determination after the load and store instructions have committed.

13. The apparatus of claim 11 , wherein for each pair of load and store instructions, the conditioning of store-to-load forwarding is further conditioned on the corresponding record being a sufficient record in that the record is a cumulative indicator of a plurality of past instances in which the load instruction was executed.

14. The apparatus of claim 11 , wherein the record is a cumulative indicator of the propriety of store-to-load forwarding of a plurality of past instances in which the load instruction was executed.

15. The apparatus of claim 14 , wherein the cumulative indicator is a function of instances in which forwarding that did not occur would have been valid, instances in which forwarding that did not occur would not have been valid, instances in which forwarding that did occur was verified to be valid, and instances in which forwarding that did occur resulted in an abort.

16. The apparatus of claim 11 , wherein separate records of the propriety of store-to-load forwarding for the load instruction are kept for different execution environments in which the load instruction was executed.

17. The apparatus of claim 11 , wherein the cumulative indicator includes a translation context (TC) for the load instruction, the method further comprising:
comparing the recorded TC with the load instruction's TC, and when they do not match, refraining from forwarding and sourcing the load data from the cache;
wherein a TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a translation regime (TR), a combination of two or more of the ASID, VMID, and TR or PM, or a hash and/or subset of the ASID, VMID, and/or TR or PM.

18. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a superscalar, out-of-order, speculative executing processor to include:
an out-of-order, speculative-executing execution pipeline;
a memory dependence predictor (MDP) that predicts whether load instructions could validly forward store data from earlier store instructions;
wherein the predictions are based upon records of one or more previous instances of the load instructions executing;
MDP training logic that, after a load instruction and store instruction progress far enough through an execution pipeline that they can no longer be aborted by an earlier instruction or cause an abort themselves, determines whether a committed load instruction received, or could have received, valid store data from the store instruction, and causes that determination to be

Assignees

• Ventana Micro Systems Inc

Inventors

• Favor John G
• Srinivasan Srivatsan

Classifications

• G06F21/54 Primary

  by adding security routines or objects to programs · CPC title

• G06F21/53

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title

• G06F21/554

  involving event detection and direct action · CPC title

• G06F21/556

  involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title